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freescale semiconductor data sheet: advance information document number: PXD20 rev. 2, 04/2012 this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. PXD20 416 tepbga 27 mm x 27 mm 176 lqfp 24 mm x 24 mm 208 lqfp 28 mm x 28 mm ? freescale semiconductor, inc., 2011?2012. all rights reserved. preliminary?subject to change without notice the PXD20 represents a new generation of 32-bit microcontrollers targeting single-chip industrial hmi applications. PXD20 devices are part of the px family of power architecture ? -based devices. this family has been designed with an emphasis on providing cost-effective and high quality graphics capabilities. PXD20 devices contain 2 mb inte rnal flash memory. serial flash memory and dram interfaces are provided to allow even greater system flexibility. the PXD20: ? includes 2 mb internal flash memory, 1 mb internal graphics sram, and 64 kb system sram ? offers high processing performance operating at speeds up to 125 mhz ? is optimized for low power consumption the PXD20 is designed to reduce development and production costs of tft-based displays by providing a single-chip solution with the processing and storage capacity to host and execute real-time application software and drive tft displays directly. the PXD20 features a 2d open vg 1.1 graphi cs accelerator, video input unit (viu2) and two on-chip display control units (dcu3 and dculite) designed to drive two color tft displays simultaneously. the PXD20 includes a enhanced quadspi serial flash contro ller and an optional dram controller allowing graphics ram expansion externally. the PXD20 is compatible with the existing development infrastructure of current powe r architecture devices and are supported with software drivers, operating systems and configuration code to assist with application development. PXD20 microcontroller data sheet 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pinout and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . 24 2.1 176 lqfp package pinout . . . . . . . . . . . . . . . . . . . . . . 24 2.2 208 lqfp package pinout . . . . . . . . . . . . . . . . . . . . . . 25 2.3 416 tepbga package pinout?40 to 105c . . . . . . . . . 26 2.4 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3 system design information. . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.1 power-up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4 electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 63 4.4 recommended operating conditions . . . . . . . . . . . . . . 64 4.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 66 4.6 emi (electromagnetic interference) characteristics . . . 70 4.7 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.8 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . 75 4.9 reset electrical characteristics . . . . . . . . . . . . . . . . . 84 4.10 fast external crystal osci llator (4?16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.11 slow external crystal osci llator (32 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.12 fmpll electrical characteristics. . . . . . . . . . . . . . . . . . 88 4.13 fast internal rc oscill ator (16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.14 slow internal rc oscill ator (128 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.15 flash memory electrical characteristics . . . . . . . . . . . . 90 4.16 adc parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.17 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.18 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 2 1 overview 1.1 device comparison table 1. PXD20 family feature set feature PXD20 package 176 lqfp 208 lqfp 416 mapbga cpu e200z4d 4 kb instruction-cache 16-entry memory management unit (mmu) floating point unit (fpu) signal processing extension (spe) execution speed static?125 mhz flash memory (ecc) 2 mb ram (ecc) 64 kb on-chip graphics ram (no ecc) 1 mb mpu 16 entry edma 16 channels dram controller no yes openvg graphics accelerator (gfx2d) yes (openvg 1.1) display control unit (dcu3) yes display control unit lite (dculite) no yes timing controller (tcon) and rsds interface no yes video input unit (viu2) yes quadspi serial flash interface yes stepper motor controller (smc) 4 motors 6 motors stepper stall detect (ssd) yes sound generator module (sgm) yes 32 khz external crystal oscillator yes real time counter and autonomous periodic interrupt (rtc/api) ye s periodic interrupt timer (pit) 8 ch, 32-bit software watchdog timer (swt) yes system timer module (stm) 4 ch, 32-bit timed i/o 20 ch, 16-bit: ic / oc / opwm 8 ch, 16-bit: ic / oc 4 ch, 16-bit: ic / oc / opwm / qdec
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 3 analog-to-digital converter (adc) 16 channels, 10-bit 20 channels, 10-bit can (64 mailboxes) 3 can can sampler yes serial communication interface 3 lin 4 lin spi 2 spi 3 spi i 2 c 4 gpio 128 150 177 debug nexus class 3 (4 ? mdo) nexus class 3 (12 ? mdo) table 1. PXD20 family feature set (continued) feature PXD20 package 176 lqfp 208 lqfp 416 mapbga
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 4 1.2 block diagram figure 1. PXD20 block diagram rsds tcon smd 6x ssd crossbar switch (xbar) PXD20 block diagram vreg oscillator interrupt system fmpll x 2 debug jtag controller e200z4d core mmu z160 rsds rtc/32 khz 2d gfx tcon oscillator viu2 dcu lite dcu nexus class 3+ (4 kb i-cache) 16-ch dma crossbar masters memory protection unit (mpu) pit swt stm 2 mb flash ecc 64 kb sram 1 mb graphics sram rle decode quad spi v02 dram interface communications i/o system crossbar slaves boot assist module (bam) emios a 16-ch emios b 16-ch 3x can 4x uart/lin 3x spi 4x i 2 c sgm 20-ch adc 10-bit pbridge adc ? analog-to-digital converter can ? controller area network controller dcu ? display control unit dma ? direct memory access controller dram ? dynamic random-access memory ecc ? error correction code emios ? timed input/output fmpll ? frequency-modulated phase-locked loop gfx ? openvg graphics accelerator i 2 c ? inter-integrated circuit controller jtag ? joint test action group interface mmu ? memory management unit pbridge ? peripheral i/o bridge pit ? periodic interrupt timer rle ? run length encoding rtc ? real time clock rsds ? reduced-swing differ ential sgnal interface sgm ? sound generator module smd ssd ? stepper motor driver/stepper stall detect spi ? serial peripheral interface controller sram ? sraric random-access memory stm ? system timer module swt ? software watchdog timer tcon ? timing controller uart/lin ? universal asynchronous receiver/transmitter/ local interconnect network viu2 ? video input unit vle ? variable-length execution set vreg ? voltage regulator
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 5 1.3 feature list ? dual-issue, 32-bit power architecture book e compliant cpu core complex (e200z4d) ? memory management unit (mmu) ? 4 kb, 2/4-way instruction cache ? 2 mb on-chip ecc flash memory with: ? flash memory controller ? prefetch buffers ? 64 kb on-chip ecc sram ? 1 mb on-chip non-ecc graphics sram wi th two-port graphics sram controller ? memory protection unit (mpu) with up to 16 region descriptors and 32-byte region granularity to provide basic memory access permission and ensure sepa ration between different codes and data ? interrupt controller (intc) with 181 peripheral interrupt sources and eight software interrupts ? two frequency-modulated phase-locked loops (fmplls) ? primary fmpll (fmpll0) provides a system clock up to 125 mhz ? auxiliary fmpll (fmpll1) is available for use as an alternate, modulated or non-modulated clock source to emios modules, quadsp i and as alternate clock to the dcu and dcu-lite for pixel clock generation ? crossbar switch architecture enables concurrent access of peripherals, flash memory or ram from multiple bus masters ? 16-channel enhanced direct memory access controller (edm a) with multiple transfer request sources using a dma channel multiplexer ? boot assist module (bam) with 8 kb dedicated rom for embedded boot code supports boot options including download of boot code via a serial link (can or sci) ? two display control units (dcu3 and dculite) for direct drive of up to two tft lcd displays up to xga resolution ? timing controller (tcon) and rs ds interface for the dcu3 module ? 2d openvg 1.1 and raster gr aphics accelerator (gfx2d) ? video input unit (viu2) supporting 8/10-bit itu656 video input, yuv to rgb conversion, video down-scaling, de-interlacing, contrast adjustme nt and brightness adjustment. ? dram controller supporting ddr1, ddr2, lpddr1 and sdr drams ? stepper motor controller (smc) ? high-current drivers for as many as six stepper motors driven in full dual h-bridge configuration ? stepper motor return-to-zero and stall detection module ? stepper motor short circuit detection ? sound generator module (sgm) ? 4-channel mixer ? supports pcm wave playback and synthesized tones ? optional pwm or i 2 s outputs ? two 16-channel enhanced modular input output system (emios) modules ? support a range of 16-bit input capture, output co mpare, pulse width modulation and quadrature decode functions ? 10-bit analog-to-digital converter (adc) with a maximum conversion time of 1 ? s ? up to 20 internal channels ? up to 8 external channels ? three deserial serial peripheral interface (dspi) modules for full-duple x, synchronous, co mmunications with external devices ? quadspi serial flash memory controller ? supports single, dual and quad io serial flash memory
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 6 ? interfaces to external, memory -mapped serial flash memories ? supports simultaneous addressing of 2 external se rial flashes to achieve up 80 mb/s read bandwidth ? rle decoder supporting memory to memory decoding of rle data in conjunction with edma ? four local interconnect network (linflex) controller modules ? capable of autonomous message handling (master), autonomous header handling (slave mode), and uart support ? compliant with lin protocol rev 2.1 ? three controller-area network (flexcan) modules ? compliant with the can protocol version 2.0 c ? 64 configurable buffers ? programmable bit rate of up to 1 mb/s ? four inter-integrated circuit (i 2 c) internal bus controllers with master/slave bus interface ? low-power loop controlled pierce crystal oscillat or supporting 4?16mhz extern al crystal or resonator ? real time counter (rtc) with clock source from internal 128 khz or 16 mhz oscillator supporting autonomous wake-up with 1 ms resolution with maximum timeout of 2 seconds ? support for real time counter (rtc) with clock source from external 32 khz crystal oscillator, supporting wake-up with 1 s resolution and maximum timeout of one hour ? rtc optionally clocked by fast 4?16 mhz external oscillator ? system timers: ? four-channel 32-bit system timer module (stm) ? eight-channel 32-bit periodic interrupt timer (pit) module (including adc trigger) ? software watchdog timer (swt) ? system integration unit lite (siul) module to manage external interrupts, gpio and pad control ? system status and configuration module (sscm) ? provides information for identification of the device, last boot mode, or debug status ? provides an entry point for the censorship password mechanism ? clock generation module (mc_cgm) to generate system clock sources and provide a unified regist er interface, enabling access to all clock sources ? clock monitor unit (cmu) ? monitors the integrity of the fast (4?16 mhz) exte rnal crystal oscillator and the primary fmpll (fmpll0) ? acts as a frequency meter, measuring the frequency of one clock source and compar ing it to a reference clock ? mode entry module (mc_me) ? controls the device power mode, i.e., run, halt, stop, or standby ? controls mode transition sequences ? manages the power control, voltage regulator, clock generation and clock management modules ? power control unit (mc_pcu) to implement standby mode entry/exit and control connections to power domains ? reset generation module (mc_rgm) to manage reset as sertion and release to the device at initial power-up ? nexus development interface (ndi) per ieee-isto 5001-2008 class 3 standard with additional class 4 features: ? watchpoint triggering ? processor overrun control ? device/board boundary-scan testing supported per joint te st action group (jtag) of ieee (ieee 1149.1) ? on-chip voltage regulator controller for regulating the 3.3?5 v supply voltage down to 1.2 v for core logic (requires external ballast transistor) ? package: 1 ? 176 lqfp, 0.5 mm pitch, 24 mm ? 24 mm outline 1. see the device comparison table for package offerings for each device in the family.
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 7 ? 208 lqfp, 0.5 mm pitch, 28 mm ? 28 mm outline ? 416 tepbga, 1mm ball pitch, 27 mm ? 27 mm outline 1.4 feature details 1.4.1 low-power operation the PXD20 is designed for optimized low-power operation an d dynamic power management of the cpu and peripherals. power management features include software-controlled clock gating of peripherals and multiple power domains to minimize leakage in lo w-power modes. there are three low-power modes: ? standby ?stop ? halt and five dynamic power modes ? run[0..3] and drun. all low-power modes use clock gating to halt the clock for all or part of the device. standby mode turns off the power to the majority of the chip to offer the lowest power consumption mode. the device can be awakened from standby mode via from any of up to 23 i/o pins, a reset or from a periodic wake-up using a low power oscillator. if required, it is possible to enable the internal 16 mhz osci llator, the external 4?16 mhz oscillator an d the external 32 khz oscillator. in standby mode the contents of the cpu, on-chip peripheral registers and potentially some of the volatile memory are lost. the two possible configurations in standby mode are: ? the device retains 64 kb of the on-chip sram, bu t the content of the graphics sram is lost. ? the device retains 8 kb of the on-chip sram, but the content of the graphics sram is lost. stop mode maintains power to the entire device allowing the re tention of all on-chip registers and memory, and providing a faster recovery low power mode than th e lowest-power standby mode. there is no need to reconfigure the device before executing code. the clocks to the cpu and peripherals are halted and can be optionally stopped to the oscillator or pll at the expense of a slower start-up time. stop is entered from run mode only. wake- up from stop mode is triggered by an ex ternal event or by the internal periodic wake-up, if enabled. run modes are the main operating modes where the entire device can be powered and clocked and from which most processing activity is done. four dynamic run modes are supported?run0 - run3. the ability to configure and select different run modes enables different clocks and power configurations to be sup ported with respect to each other and to allow switching between different operating condi tions. the necessary peripherals, clock sources, clock speed and system clock prescalers can be independently configur ed for each of the four run modes of the device. halt mode is a reduced activity, low power mode intended for modera te periods of lower processing activity. in this mode the cpu system clocks are stopped but user-select ed peripheral tasks can continue to run. it can be configured to provide more efficient power management features (switch- off pll, flash memory, main regulator, etc.) at the cost of longer wake up latency. the system returns to run mode as soon as an event or interrupt is pending. table 2 summarizes the operating modes of the PXD20.
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 8 additional notes on low power operation: ? fast wake-up using the on-chip 16 mhz internal rc oscillator allows rapid execution from ram on exit from low power modes ? the 16 mhz internal rc oscillator supports low speed code execution and clocking of periph erals when it is selected as the system clock and can also be us ed as the pll input clock source to provi de fast start-up without the external oscillator delay ? the device includes an internal voltage regul ator that includes th e following features: table 2. operating mode summary 1 1 table key: on?powered and clocked op?optionally configurable to be enabled or disabled (clock gated) cg?clock gated, powered but clock stopped off-?powered off and clock gated fp?vreg full performance mode lp?vreg low power mode, reduced output capability of vreg but lower power consumption var?variable duration, based on the required reconfiguration and execution clock speed bam?boot assist module software and hardware used for device start-up and configuration operating mode soc features clock sources periodic wake-up wake-up input vreg mode wake-up time 2 2 a high level summary of some key durations that need to be considered when recovering from low power modes. this does not account for all durations at wake up. other delays will be necessary to consider including, but not limited to the external supply start-up time. irc wake-up time must not be added to the overall wake-up time as it starts in parallel with the vreg. all other wake-up times must be added to determine the total start-up time. cpu gfx accelerator dram controller peripherals flash ram graphics ram primary pll auxiliary pll 16 mhz irc 4?16 mhz osc 128 khz irc 32 khz x osc vreg start-up irc wake-up flash recovery osc stabilization pll lock s/w reconfig mode switch over run on op op op 3 3 either 64 kb or 8 kb available. on op op on op on op ? ? fp ? ? ? ? ? ? ? halt cg op op op 3 on op op on op on op op op fp ? ? ? ? ? ? tbd stop cg cg cg op 3 on cg cg op op on op op op lp 350 s 4 s 20 s 1 ms 200 s ? 24 s standby off off off 64 kb 4 4 64 kb of the ram contents is retained, but not accessible in standby mode. off off off op op op op op op lp 350 s 8 s 100 s 1 ms 200 s var 28 s off off off 8 kb 5 5 8 kb of the ram contents is retained , but not accessible in standby mode. off off off op op op op op op lp 200 s 8 s 100 s 1 ms 200 s var 28 s por 500 s 8 s 100 s 1 ms 200 s bam 6 6 dependent on boot option after reset.
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 9 ? regulates input to generate all internal supplies ? manages power gating ? external ballast transistor for high power regulator ? low-power and ultra-low-power regulators support operation when in stop and standby modes, respectively, to minimize power consumption ? startup on-chip regulators in <350 s for rapid exit of stop and standby modes ? low voltage detection on main supply and 1.2 v regulated supplies. 1.4.2 e200z4d core the e200z4d power architecture core provides the following features: ? dual issue, 32-bit power architecture book e compliant cpu ? implements the vle apu for reduced code footprint ? in-order execution and retirement ? precise exception handling ? branch processing unit ? dedicated branch address calculation adder ? branch target prefetching using 8-entry btb ? supports independent in struction and data accesses to different memory subsystems, such as sram and flash memory via independent instruction and data bius. ? load/store unit ? 2 cycle load latency ? fully pipelined ? big and little endian support ? misaligned access support ? 64-bit general purpose register file ? dual ahb 2.v6 64-bit system buses ? memory management unit (mmu) with 16-entry fully-associative tlb and multiple page size support ? 4 kb, 2/4-way set associative instruction cache ? signal processing extension (spe1.1) apu supporting simd fixed-point opera tions using the 64-bit general purpose register file. ? embedded floating-point (efp2) apu supporting scalar and vector simd single-precision floating-point operations, using the 64-bit general purpose register file. ? nexus class 3 real-time development unit ? dynamic power management of execution units, cache and mmu 1.4.3 crossbar switch (xbar) the xbar multi-port crossbar switch supports simultaneous conn ections between seven master ports and eight slave ports. the crossbar supports a 32 -bit address bus width and a 64-bit data bus width. the crossbar allows concurrent transactions to occur from any master port to any slave port but one of those transfers must be an instruction fetch from internal flash. if a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master an d grants it ownership of the slave port. all other masters requesting that slave por t are stalled until the higher priority master completes its transactions. requesting mast ers having equal prio rity are granted acces s to a slave port in round-robin fash ion, based upon the id of the la st master to be granted access. the crossbar provides the following features:
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 10 ? seven master ports: ? e200z4d core instruction port ? e200z4d core complex load/store data port ? edma controller ?dcu ? dcu-lite ?viu ? 2d graphics accelerator (gfx2d) ? seven slave ports: ? platform flash controller (2 ports) ? platform sram controller ? graphics sram controller (2 ports) ? quadspi serial flash co ntroller and rle decoder ? peripheral bridge ? 32-bit internal address bus, 64-bit internal data bus ? programmable arbitration priority ? requesting masters can be treated with equal priority and will be granted access to a slave port in round-robin fashion, based upon the id of the last master to be granted access or a priority order can be assigned by software at application run time ? temporary dynamic priori ty elevation of masters 1.4.4 enhanced direct memory access (edma) the edma module is a controller capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. the hardware micro architecture includes a dma engine which performs source and destination address calculations, and the actual data moveme nt operations, along with an sram-based memory containing the transfer control descriptor s (tcd) for the channels. this implementation is utilized to minimize th e overall block size. th e edma module provides the following features: ? 16 channels support independent 8-, 16- or 32-bit single value or block transfers ? supports variable sized qu eues and circular queues ? source and destination addre ss registers are independently configured to post-increment or remain constant ? each transfer is initiated by a peripheral, cpu, periodic timer in terrupt or edma channel request ? each dma channel can optionally send an interrupt request to the cpu on completion of a single value or block transfer ? dma transfers possible between system memories, quadspi, rle decoder, spis, i 2 c, adc, emios and general purpose i/os (gpios) ? programmable dma channel mux allows assignment of a ny dma source to any available dma channel with up to a total of 64 potential request sources. 1.4.5 interrupt controller (intc) the intc (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard r eal-time systems. for high priority interrupt requests, the time from the assertion of the interrupt request from th e peripheral to when the proc essor is executing the interrupt serv ice routine (isr) has been minimized. the intc provides a unique vector for each interrupt request source for quick determination of which isr needs to be ex ecuted. it also provides an ample number of priorities so tha t
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 11 lower priority isrs do not dela y the execution of higher priority isrs. to allow the approp riate priorities for each source of interrupt request, the priority of each in terrupt request is software configurable. when multiple tasks share a resour ce, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by pr oviding a modifiable priority mask, the pr iority can be raised temporarily so that all tasks which share the resource can not preempt each other. multiple processors can assert interrupt requests to each othe r through software settable interrupt requests. these same softwa re settable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. the high pr iority portion is initiated by a peripheral interrupt request, but then the isr asserts a software settable interrupt request to finish the servicing in a lower priority isr. therefor e these software settable interr upt requests can be used instead of the peripheral isr schedu ling a task through the rtos. the intc provides the following features: ? unique 9-bit vector for each of the po ssible 128 separate interrupt sources ? eight software triggerable interrupt sources ? 16 priority levels with fixed ha rdware arbitratio n within priority levels for each interrupt source ? ability to modify the isr or task priority. ? modifying the priority can be used to implement the priority ceiling pr otocol for accessing shared resources. ? external non maskable interrup t directly accessing the main cpu critical interr upt mechanism ? 32 external interrupts 1.4.6 quadspi serial flash memory controller the quadspi module enables use of external serial flash memories supporting single, dual and quad modes of operation. it features the following: ? maximum serial clock frequency 80 mhz ? memory mapped read access for ahb crossbar switch masters ? automatic serial flash read comm and generation by cpu, edma, dcu, or dcu-lite read access on ahb bus ? supports single, dual and quad serial flash read commands ? simultaneous mode: ? supports concurrent read of two external serial flashes ? the quad data streams from the two flashes can be reco mbined in the quadspi to ach ieve up to 80 mb/s read bandwidth with 80 mhz serial flash ?16 ? 64-bit buffer with speculative fetch and buffer flush mechanisms to maximize read bandwidth of serial flash ? dma support ? all serial flash program, eras e, read and configuration commands available via ip bus interface. 1.4.7 system integration unit lite (siul) the siul controls mcu reset configurati on, pad configuration, external interr upt, general purpose i/o (gpio), internal peripheral multiplexing, and the system reset operation. the gpio features the following: ? up to four levels of internal pin multiplexing, allowing ex ceptional flexibility in the allocation of device functions for each package ? centralized general purpose input output (gpio) control ? all gpio pins can be independently configured to support pull-up, pull down, or no pull ? reading and writing to gpio supported both as individual pins and 16-bit wide ports ? all peripheral pins can be alternatively configured as bot h general purpose input or output pins except adc channels which support alternative configuration as general purpose inputs
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 12 ? direct readback of the pin value supporte d on all digital output pins through the siu ? configurable digital input filter that can be applied to up to 24 general purpose input pins for noise elimination on external interrupts ? register configuration protect ed against change with soft lock for temporary guard or hard lock to prevent modification until next reset. 1.4.8 on-chip flash memory with ecc the PXD20 microcontroller has the following flash memory features: ? 2 mb of flash memory ? typical flash memory access time: 0 wa it-state for buffer hits, 3 wait-states for page buffer miss at 125 mhz ? two 4 128-bit page buffers with programmable prefetch control ? one set of page buffers can be allocated for code-only, fixed partitions of code and data, all available for any access ? one set of page buffers allocated to display co ntroller units, graphics a ccelerator and the edma ? 64-bit ecc with single-bit correction, double-bit detection for data integrity ? small block flash arrangement to sup port features such as boot block, eepro m emulation, operating system block. ?8 ? 16 kb ?2 ? 64 kb ?2 ? 128 kb ?6 ? 256 kb ? hardware managed flash writes, erase and verify sequence ? censorship protection scheme to prevent flash content visibility 1.4.9 static random-access memory (sram) the PXD20 microcontroller has 64 kb general-pur pose on-chip sram with the following features: ? typical sram access time: 1 wait-st ate for reads and 32-bit writes ? 32-bit ecc with single-bit correction, double bit detection for data integrity ? supports byte (8-bit), half word (16-bit), word (32-bit) a nd double-word (64-bit) writes for optimal use of memory ? user transparent ecc encoding and decodi ng for byte, half word, and word accesses ? separate internal power domains applied to 56 kb and 8 kb sram blocks during standby modes to retain contents during low power mode. 1.4.10 on-chip graphics sram the PXD20 microcontroller has 1 mb on-chip gr aphics sram with the following features: ? two crossbar slave ports: ? one dedicated to the 2d grap hics accelerator (gfx2d) access ? one dedicated to all other crossbar masters ? usable as general purpose sram ? supports byte (8-bit), half word (16-bit), word (32-bit) a nd double-word (64-bit) writes for optimal use of memory ? ram controller with hardware ram fill function su pporting all-zeroes or all-ones sram initialization ? independent data buffers (one per ahb port) for maximum system performance ? optimized for burst tr ansfers (read + write) ? programmable read pr efetch capabilities
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 13 1.4.11 memory protection unit (mpu) the mpu features the following: ? sixteen region descriptors for per master protection ? start and end address defined with 32-byte granularity ? overlapping regions supported ? protection attributes can optionally include process id ? protection offered for 4 concurrent read ports ? read and write attributes for all masters ? execute and supervisor/user mode attributes for processor masters 1.4.12 2d graphics accelerator (gfx2d) ? native vector graphics rendering ? compatible with openvg1.1 ? complete hardware openvg 1.1 rendering pipeline ? both geometry and pixel processing ? adaptive processing of b ezier curves and strokes ? 16-sample edge anti-aliasing ? high image quality, font scalability, etc. ?4 ? rotated grid supersampl ing (rgss) aa for flash ? 3d perspective texturing, reflections, and shadowing ? shading (linear or radial gradient) ? separate 2d engine for bitb lt, fill and rop operations ? significant performance improvement when compared to software or 3d gpu-based openvg implementations 1.4.13 display control unit (dcu3) the dcu3 is a display controller designed to drive tft lcd displays up to wvga resolution using direct blit graphics and video. the dcu3 generates all the necessary signals required to drive the tft lcd displays: up to 24-bit rgb data bus, pixel clock, data enable, horizontal-sync and vertical-sync. the flexible architecture of the dcu3 enab les the display of openvg-rendered frame buffer content and di rect blit rendered graphics simultaneously. an optional timing controller (tcon) and rsds interface is avai lable to directly drive the row and column drivers of a display panel. internal memory resource of th e device allows to easily handle complex graphics contents (pictures, icons, languages, fonts). the dcu3 supports 4-plane ble nding and 16 graphics layers. control descriptor s (cds) associated with each of the 16 layers enable effective merging of different reso lutions into one plane to optimize use of internal memory buffers. a layer may be constructed from graphic content of various resolutions including indexed colors of 1, 2, 4 and 8 bpp, direct colors of 16, 24 and 32 bpp, and a yuv 4:2:2 color space. the ability of the dcu3 to handle input data in resolutions as low as 1bpp, 2bpp and 4bpp enables a highly efficient us e of internal memory resources of the PXD20. a special tiled mode can be enabled on any of the 16 layers to repeat a pattern optimizing graphic memory usage. a hardware cursor can be managed independently of the layers at blending level increasing the efficient use of the internal dcu3 resources.
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 14 to secure the content of all cri tical information to be displayed, a safety mode can be activated to check the integrity of cri tical data along the whole system data path from the memory to the tft pads. the dcu3 features the following: ? display color depth: up to 24 bpp ? generation of all rgb an d control signals for tft ? four-plane blending ? maximum number of input layers: 16 (fixed priority) ? dynamic look-up-table (color and gamma look-up) ? ?? blending range: up to 256 levels ? transparency mode ? gamma correction ? tiled mode on all the layers ? hardware cursor ? supports ycrcb 4:2:2 input data format ? rle decode inline supporting direct read of rle compressed images from system memory ? critical display content integrity monitoring for functional safety support ? internal direct memory access (dma) module to transf er data from internal and / or external memory. the dcu3 also features a parallel data in terface (pdi) to receive external digital vi deo or graphic content into the dcu3. the pdi input is directly injected into the dcu3 background plane fifo. when the pdi is activated, all the dcu3 synchronization is extracted from the external vi deo stream to guarantee the synchronization of the two video sources. the pdi can be used to: ? connect a video camera output directly to the pdi ? connect a secondary display driver as slave with a minimum of extra cost ? connect a device gathering various video sources ? provide flexibility to allow the dcu to be us ed in slave mode (external synchronization) the pdi features the following: ? supported color modes: ? 8-bit mono ? 8-bit color multiplexed ? rgb565 ? 16-bit/18-bit raw color ? supported synchronization modes: ? embedded itu-r bt.656-4 (rgb565 mode 2) ? hsync, vsync ? data enable ? direct interface with dcu3 background plane fifo ? synchronization generation for the dcu3 1.4.14 display control unit lite (dculite) the dculite is a display controller desi gned to enable the PXD20 to drive a second tft lcd display up to xga resolution using direct blit graphics and video. th e dculite includes all features of the dc u3, including the pdi with the following exceptions: ? reduced from 4-plan e to 2-plane blending ? reduced from 16 layers to 4 layers ? reduced clut size
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 15 1.4.15 timing controller (tcon) and rsds interface the tcon enables direct drive of the row and column drivers of display panels enabling emulation of tcon ics used in display panels. ? programmable timing generation unit featuring 12 waveform generators allowing high degree of flexibility in panel waveform generation ? reduced swing differential signaling (rsd s) interface for rgb data and pixel clock ? conforms to ?rsds ?intra panel? interface spec ification? rev. 1.0 (national semiconductor) 1.4.16 rle decoder the rle decoder is a crossbar slave shari ng a slave port with the qu adspi module. the platform edma is used to stream compressed image data into and extract deco mpressed data out of the rle decoder. ? lossless decompression ? pixel formats supported: 8bpp, 16bpp, 24bpp and 32bpp ? ahb mapped read and write registers in rle_dec to achieve higher throughput ? programmable fill levels of read and wr ite buffers for initiating burst transfers ? crop feature: support for selectively reading out a part of decompressed image data taking complete compressed data for the full image as input. 1.4.17 dram controller the dram controller is a multi-port dram controller su pporting sdr, lpddr1, ddr-1, and ddr-2 memories. the dram controller listens to the incoming requests to the seven buse s in parallel and then sends commands to the dram from the highest priority bus at the current time the seven incoming 64-bit buses are: ?dcu3 ?dculite ? e200z4d core - instruction bus ? e200z4d core - data bus ?viu2 ?gfx2d ?edma the dram controller f eatures the following: ? supports cas latency of 2, 3, and 4 clock cycles. ? master buses ? 7 incoming master buses ? supports 16-byte and 32-byte bursts ? supports byte enables ? supports 4-bit priority signal for each bus ? write buffer contains five 32-byte entries ? supports 16-wide and 32-wide sdr, ddr1, ddr2 and lpddr1 dram devices ? controller supports one chip select, 8-bank dram system ? supports dynamic on-die termination in the host device and in the dram. ? supports memory sizes as small as 64mbit
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 16 1.4.18 video input unit (viu2) the viu2 is a crossbar master module accep ting an itu656 compatible video input st ream on a parallel interface, converting the pixel data to rgb or yuv format and transferring the video image to internal frame buffer memory or external dram if available. ? supports 8-bit/10-bit itu656 video input ? output formats: ? rgb888 ? rgb565 ? 8-bit monochrome ? ycrcb 4:2:2 ? video downscaling ? contrast and brightness adjustment ? de-interlace for interlaced video image ? internal dma engine for data transfer to memory 1.4.19 boot assist module (bam) the bam is a block of read-only memory that is programm ed once by freescale. the bam program is executed every time the mcu is powered-on or reset in normal mode. the ba m supports different modes of booting. they are: ? booting from internal flash memory ? serial boot loading (a program is downloaded into ram via can or lin and then executed) ? booting from external memory additionally the bam: ? enables and manages the transition of th e mcu from reset to user code execution ? configures device for serial bootload ? enables multiple bootcode starting locations out of rese t through implementation of search for valid reset configuration halfword ? enables or disables software watchdog timer out of rese t through bam read of reset configuration halfword option bit 1.4.20 enhanced modular inpu t/output system (emios) this device has two emios modules, each with 16 channels supporting a range of 16-bit inpu t capture, output compare, pulse width modulation, and quadrature decode functions. ? selectable clock source from primary fmpll, secondary fm pll, external 4?16 mhz oscillator or 16 mhz internal rc oscillator on a per module basis ? timed i/o channels with 16-bit counter resolution ? buffered updates ? support for shifted pwm outputs to minimize occurrence of concurrent edges ? edge aligned output pulse width modulation ? programmable pulse period and duty cycle ? supports 0% and 100% duty cycle ? shared or independent time bases ? programmable phase shift between channels ? 4 channels of quadrature decode ? dma transfer support
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 17 1.4.21 analog-to-digital converter (adc) the adc features the following: ? 10-bit a/d resolution ? 0?5 v or 0?3.3 v common mode conversion range ? supports conversions speeds of up to 1 ? s ? 20 internal and 8 external channels support ? up to 20 single-ended inputs channels ? 10 channels configured as input only pins ? 10-bit 2 counts accuracy (tue) ? 10 channels configured to have alternate function as general purpose input/output pins ? 10-bit 3 counts accuracy (tue) ? external multiplexer support to increase up to 27 channels ? automatic 1 8 multiplexer control ? external multiplexer connected to a dedicated input channel ? shared register between the 8 external channels ? result register available for every non-multiplexed channel ? configurable left or right aligned result format ? supports for one-shot, scan and injection conversion modes ? injection mode status bit implemented on adjacent 16-bit register for each result ? supports access to result and injection status with single 32-bit read ? independently enabling of function for channels: ? pre-sampling ? offset error cancellation ?offset refresh ? conversion triggering support ? internal conversion triggering from periodic interrupt timer (pit) ? four configurable analog comparator channels offering range comparison with triggered alarm ? greater than ? less than ? out of range ? all unused analog pins available as general purpose input pins ? selected unused analog pins available as general purpose pins ? power down mode ? optional support for dma transfer of results 1.4.22 serial peripheral interface (spi) the spi modules provide a synchronous serial interface fo r communication between the mcu and external devices. the spi features: ? full duplex, synchronous transfers ? master or slave operation ? programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? programmable transfer baud rate
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 18 ? programmable data frames from 4 to 16 bits ? up to 3 chip select lines available, de pending on package and pin multiplexing, enab le 8 external devices to be selected using external muxing from a single spi ? eight clock and transfer attributes registers ? chip select strobe available as alternate function on one of the chip select pins for de-glitching ? fifos for buffering up to 4 transfer s on the transmit and receive side ? general purpose i/o functionality on pins when not used for spi ? queueing operation possible through use of edma 1.4.23 controller area network (can) module the PXD20 includes up to three controller area network (can ) modules. the can module is a communication controller implementing the can prot ocol according to bosch specificat ion version 2.0b. the can protoc ol was designed to be used primarily as a vehicle serial data bus, meet ing the specific requirements of this fiel d: real-time processing, reliable operati on in the emi environment of a vehicle, cost -effectiveness and required bandwidth. each can module offers the following: ? compliant with can protocol specification, version 2.0b active ? 64 mailboxes, each configurable as transmit or receive ? mailboxes configurable while module remains synchronized to can bus ? transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to messa ge id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort procedure and notification ? receive features ? individual programmable filters for each mailbox ? 8 mailboxes configurable as a 6-entry receive fifo ? 8 programmable acceptance filters for receive fifo ? programmable clock source ? system clock ? direct oscillator clock to avoid pll jitter ? listen only mode capabilities ? can sampler ? can catch the 1st message sent on the can network while the mcu is stopped. this guarantees a clean startup of the system without missing messages on the can network. ? the can sampler is connected to one of the can rx pins. 1.4.24 serial communication interface module (uart) the PXD20 devices include up to four uart modules and support for uart master mode, uart slave mode and uart mode. the modules are uart state machine compliant to the lin 1.3 and 2.0 and 2.1 specifications and handle uart frame transmission and reception without cpu in tervention. the serial communication interf ace module offers the following: ? uart features: ? full-duplex operation ? standard non return-to-ze ro (nrz) mark/space format
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 19 ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt driven operation with 4 interrupts sources ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud-rate m odulus counter and 16-bit fractional ? 2 receiver wake-up methods ? lin features: ? autonomous lin frame handling ? message buffer to store identif ier and up to eight data bytes ? supports message length of up to 64 bytes ? detection and flagging of lin errors ? sync field; delimiter; id parity; bit, framing; checksum and timeout errors ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features ? loop back ?self test ? lin bus stuck dominant detection ? interrupt driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? discarding of irrelevant lin resp onses using up to 16 id filters 1.4.25 inter-integrated circuit (i 2 c) controller modules the PXD20 includes four i 2 c modules. each module features the following: ? two-wire bi-directional serial bus for on-board communications ? compatibility with i 2 c bus standard ? multi-master operation ? software-programmable for one of 256 different serial clock frequencies ? software-selectable acknowledge bit ? interrupt-driven, byte-by-byte data transfer ? arbitration-lost interrupt with automatic mode switching from master to slave ? calling address identification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus-busy detection
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 20 1.4.26 system clocks and clock generation modules the system clock on the PXD20 can be de rived from an external oscillator, an on-chip fmpll, or the internal 16 mhz oscillator. the source system clock frequency can be changed via an on-chip programmable clock divider ( ? 1 to ?? 2). an additional programmable peripheral bus clock divider (ratios ? 1 to ??? ) is also available. the PXD20 has two on-chip fmplls (primary an d secondary). each features the following: ? input clock frequency from 4 mhz to 16 mhz ? lock detect circuitry continuously monitors lock status ? loss of clock (loc) detection for reference and feedback clocks ? on-chip loop filter (for improved electromagnetic inte rference performance and reduction of number of external components required) ? support for frequency ramping from pll the primary fmpll module is for use as a system clock source. the s econdary fmpll is av ailable for use as an alternate, modulated or non-modulated clock source to emios modules and as alternate clock to the dcu for pixel clock generation. the main oscillator provides the following features: ? input frequency range 4?16 mhz ? square-wave input mode ? oscillator input mode 3.3 v (5.0 v) ? automatic level control ? low power consumption ? pll reference the PXD20 also includes the following oscillators: ? 32 khz low power external oscillator for slow execution, low power, and rtc ? dedicated internal 128 khz rc oscillator for low power mode operation and self wake-up ? 10% accuracy across voltage and temp erature (after f actory trimming) ? trimming registers to support improved accuracy with in-application calibration ? dedicated 16 mhz internal rc oscillator ? used as default clock source out of reset ? provides a clock for rapid start-up from low power modes ? provides a back-up clock in the event of pll or external oscillator clock failure ? offers an independent clock source for the swt ? 5% accuracy across voltage and temp erature (after factory trimming) ? trimming registers to support frequency adjustment with in-application calibration 1.4.27 periodic interrupt timer (pit) the pit features the following: ? eight general purpose interrupt timers ? two dedicated interrupt timers for triggering adc conversions ? 32-bit counter resolution ? clocked by system clock frequency
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 21 1.4.28 real time counter (rtc) the real timer counter supports wake-up from low power modes or real time clock generation ? configurable resolution for different timeout periods ? 1 s resolution for >1 hour period ? 1 ms resolution for 2 second period ? selectable clock sources from external 32 khz crystal, external 4?16 mhz crysta l, internal 128 khz rc oscillator or divided internal 16 mhz rc oscillator 1.4.29 system timer module (stm) the stm is a 32-bit timer designed to support commonly require d system and application software timing functions. the stm includes a 32-bit up counter and fo ur 32-bit compare channels with a separate in terrupt source fo r each channel. the counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels ? independent interrupt source for each channel ? counter can be stopped in debug mode 1.4.30 software watchdog timer (swt) the swt features the following: ? watchdog supporting software activation or enabled out of reset ? supports normal or windowed mode ? watchdog timer value writable once after reset ? watchdog supports optional halting during low power modes ? configurable response on timeout: reset, interrupt, or interrupt followed by reset ? clock source: 128 khz rc oscillator 1.4.31 stepper motor controller (smc) the smc module is a pwm motor controller suitable to drive inst ruments in a cluster configuration or any other loads requiring a pwm signal. the motor controller has twelve pwm channels associ ated with two pins each (24 pi ns in total) driving up to 6 stepper motors. the smc module includes the following features: ? 10/11-bit pwm counter ? 11-bit resolution with selectable pwm dithering function ? left, right, or center aligned pwm ? output slew rate control ? output short circuit detection this module is suited for, but not limited to, driving small stepper and air core motors used in instrumentation applications. this module can be used for other motor control or pwm applications that match the frequency, resolution, and output drive capabilities of the module.
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 22 1.4.32 stepper stall de tect (ssd) module the ssd module provides a circuit to measur e and integrate the induced voltage on the non-driven coil of a stepper motor using full steps when the gauge pointer is returning to zero (rtz). the ssd module features the following: ? programmable fu ll step state ? programmable integration polarity ? blanking (recirculation) state ? 16-bit integration accumulator register ? 16-bit modulus down counter with interrupt 1.4.33 sound generator module (sgm) the sgm features the following: ? 4-channel audio mixer ? each channel capable of independent tone generation or wave playback ? individual channel volume control (8-bit resolution) ? tone mode: ? programmable tone frequency ? programmable amplitude envel ope: attack, duration and decay ? programmable number of tone pulses and inter-tone duration ? wave mode: ? one fifo per channel workin g in conjunction with edma ? supports standard audio sampling rates (4 khz, 8 khz , 11.025 khz, 16 khz, 22.050 khz, 32 khz, 44.100 khz, 48 khz) ? same sample rate applies to all channels ? 8-bit, 12-bit, 16-bit input data formats ? programmable wave duration and inter-wave duration ? repeat mode with programmab le number of wave playbacks ? sgm output: ? 16-bit pwm channel ? integrated i 2 s master interface for connec tion to external audio dac 1.4.34 ieee 1149.1 jtag controller (jtagc) jtagc features the following: ? backward compatible to standard jtag ie ee 1149.1-2001 test access port (tap) interface ? support for boundary scan testing 1.4.35 nexus development interface (ndi) the nexus 3 module is compliant with class 3 of the ieee-isto 5001-2008 standard, with additional class 4 features available. the following features are implemented: ? program trace via branch trace messagi ng (btm). branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development to ol to interpolate what transpires between the discontinuities. thus static code may be traced.
overview PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 23 ? data trace via data write messaging (dwm) and data read messaging (drm). this provi des the capability for the development tool to trace read s and/or writes to selected internal memory resources. ? ownership trace via ownership trace messa ging (otm). otm facilitates ownershi p trace by providing visibility of which process id or operating system task is activated. an ownership trace message is transmitted when a new process/task is activated, allowing the de velopment tool to trace ownership flow. ? run-time access to embedded processor memory map via the jtag port. this allows fo r enhanced download/upload capabilities. ? watchpoint messaging via the auxiliary pins ? watchpoint trigger enable of pr ogram and/or data trace messaging ? data acquisition messaging (dqm) allows code to be instrumented to export customized information to the nexus auxiliary output port. ? address translation messaging via program correlation messages displays updates to the tlb for use by the debugger in correlating virtual and ph ysical address information ? auxiliary interface for hi gher data input/output ? registers for program trace, data trace, ownership trace and wa tchpoint trigger. ? all features controllable and c onfigurable via the jtag port
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 24 2 pinout and signal descriptions 2.1 176 lqfp package pinout figure 2 shows the pinout for the 176-pin lqfp package. figure 2. 176-pin lqfp pinout PXD20 176 lqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 vss vdd12 pf15 / qspi_clk_0 / clkout / mck0 pf14 / qspi_io1_0 / mdo3 pf13 / qspi_io0_0 / mdo2 pf12 / qspi_io3_0 / mdo1 pf11 / qspi_io2_0 / mdo0 pf10 / qspi_pcs_0 / evti pg12 / cs0_1 / pdi_de vss vdde_b pf9 / scl_0 / cs1_1 / txd_1 pf8 / sda_0 / cs2_1 / rxd_1 pf7 / emios1[15] / scl_1 pf6 / qspi_io0_1 / emios1[16] / pdi17_viu9 pf5 / qspi_io1_1 / emios1[15] / pdi16_viu8 pf4 / emios1[14] / sda_1 pf3 / emios1[21] / mseo2 pf1 / emios1[20] / mseo pf0 / emios1[19] / evto pk1 / qspi_io2_1 / emios1[14] / pdi15_viu7 pk0 / emios1[18] vss pb2 / txd_0 pb3 / rxd_0 pj15 / qspi_io3_1 / emios1[9] / pdi14_viu6 pj14 / qspi_clk_1 / emios1[17] / pdi_pclk pj13 / qspi_pcs_1 / emios1[8] / pdi13_viu5 pj12 / dcu_tag pg11 / dcu_pclk pg7 / dcu_b7 pg6 / dcu_b6 pg5 / dcu_b5 pg4 / dcu_b4 pg3 / dcu_b3 pg2 / dcu_b2 vdde_b vss vdd12 pg1 / dcu_b1 / sda_3 / emios0[22] pg0 / dcu_b0 / scl_3 / emios0[21] pa15 / dcu_g7 pa14 / dcu_g6 vss nmi/pf2 cs2_0 / emios1[10] / rxd_1 / pb12 cs1_0 / emios1[11] / txd_1 / pb13 vdde_b vss vdd12 emios1[12] / sda_1 / pk10 dcu_tag / emios1[13] / scl_1 / pk11 i2s_fs / emios1[18] / sck_0 / pb9 i2s_do / emios1[19] / sout_0 / pb8 i2s_sck / emios1[20] / sin_0 / pb7 emios0[23] / emios0[21] / pdi0_viu2 / pj4 emios0[16] / emios0[20] / pdi1_viu3 / pj5 emios0[15] / emios0[19] / pdi2_viu4 / pj6 emios0[14] / emios0[18] / pdi3_viu5 / pj7 pdi_de / emios0[22] / viu_pclk / pj3 emios1[21] / cs0_0 / ph4 ma0 / sck_1 / pb4 fabm / ma1 / sout_1 / pb5 abs[0] / ma2 / sin_1 / pb6 vdde_b vss vdd12 vss xtal32 / an15 / pc15 extal32 / an14 / pc14 cs0_1 / ma2 / an13 / pc13 cs1_1 / ma1 / an12 / pc12 cs2_1/ma0/an11/pc11 i2s_do / an10_mux / pc10 an9 / pc9 an8 / pc8 vdde_a vsse_a vdda vssa an7 / pc7 an6 / pc6 an5 / pc5 an4 / pc4 an3 / pc3 an2 / pc2 an1 / pc1 an0 / pc0 vdde_b pa13 / dcu_g5 pa12 / dcu_g4 pa11 / dcu_g3 pa10 / dcu_g2 pa9 / dcu_g1 / sda_2 / emios0[19] pa8 / dcu_g0 / scl_2 / emios0[20] pa7 / dcu_r7 pa6 / dcu_r6 vss vdde_b pa5 / dcu_r5 pa4 / dcu_r4 pa3 / dcu_r3 pa2 / dcu_r2 pa1 / dcu_r1 / scl_1 / emios0[17] pa0 / dcu_r0 / sda_1 / emios0[18] pm11 / txd_2 / cntx_2 / emios0[23] pm10 / rxd_2 / cnrx_2 / emios0[16] pm9/ pdi_pclk/ sgm_mclk/ emios0[8] vdde_b vss vdd12 pd15 / m3c1p / ssd3_3 / emios0[15] pd14 / m3c1m / ssd3_2 / emios0[14] pd13 / m3c0p / ssd3_1 / emios0[13] pd12 / m3c0m / ssd3_0 / emios0[12] vssm vddm pd11 / m2c1p / ssd2_3 / emios0[11] pd10 / m2c1m / ssd2_3 / emios0[10] pd9 / m2c0p / ssd2_1 / emios0[9] pd8 / m2c0m / ssd2_0 pd7 / m1c1p / ssd1_3 pd6 / m1c1m / ssd1_2 / emios0[23] pd5 / m1c0p / ssd1_1 / emios0[16] pd4 / m1c0m / ssd1_0 / emios0[8] vssm vddm pd3 / m0c1p / ssd0_3 / emios0[9] pd2 / m0c1m / ssd0_2 / emios1[23] pd1 / m0c0p / ssd0_1 / emios1[16] pd0 / m0c0m / ssd0_0 / emios1[8] vdde_b dcu_vsync / pg8 dcu_hsync / pg9 dcu_de / pg10 emios0[8] / emios1[9] / pdi_hsync_viu1 / pj1 emios0[9] / emios1[14] / pdi_vsync_viu0 / pj2 vdde_b vss emios0[13] / emios0[17] / pdi4_viu6 / pj8 emios0[12] / emios1[22] / pdi5_viu7 / pj9 emios0[11] / emios1[17] / pdi6_viu8 / pj10 emios0[10] / emios1[15] / pdi7_viu9 / pj11 rxd_0 / cnrx_0 / pb1 txd_0 / cntx_0 / pb0 i2s_do / cnrx_1 / pb10 sgm_mclk / cntx_1 / pb11 dcu_tag / emios1[22] / pdi13_viu5 / pm5 emios1[23] / pdi14_viu6 / pm6 vss vdde_b vddr vssr vsup_test vdd12 vss vddpll vreg_bypass extal xtal vrc_ctrl reset emios1[10] / pdi8_viu0 / pk2 emios1[11] / pdi9_viu1 / pk3 emios1[12] / pdi10_viu2 / pk4 emios1[13] / pdi11_viu3 / pk5 emios1[9] / pdi12_viu4 / pk6 vss vdde_b emios1[8] / i2s_fs / pdi15_viu7 / ph5 emios1[16] / i2s_do / pdi16_viu8 / pm7 emios1[23] / i2s_sck / pdi17_viu9 / pm8 tck / ph0 tdi/ph1 tdo/ph2 tms / ph3 note: functions in bold are available only on this package.
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 25 2.2 208 lqfp package pinout figure 3 shows the pinout for the 208-pin lqfp package. figure 3. 208-pin lqfp pinout PXD20 208 lqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 dcu_vsync_tcon2 / pg8 dcu_hsync_tcon1 / pg9 dcu_de_tcon3 / pg10 emios0[8] / emios1[9] / pdi_hsync_viu1 / pj1 emios0[9] / emios1[14] / pdi_vsync_viu0 / pj2 vdde_b vss emios0[13] / emios0[17] / pdi4_viu6 / pj8 emios0[12] / emios1[22] / pdi5_viu7 / pj9 emios0[11] / emios1[17] / pdi6_viu8 / pj10 emios0[10] / emios1[15] / pdi7_viu9 / pj11 rxd_0 / cnrx_0 / pb1 txd_0 / cntx_0 / pb0 i2s_do / cnrx_1 / pb10 sgm_mclk / cntx_1 / pb11 tcon4 / rxd_3 / cnrx_2 / pm3 tcon5 / txd_3 / cntx_2 / pm4 vss vdde_b vddr vssr vsup_test vdd12 vss vddpll vreg_bypass extal xtal vrc_ctrl reset tcon6 / pdi13_viu5 / cs2_2 / pl4 tcon7 / pdi14_viu6 / cs1_2 / pl5 emios1[18] / pdi15_viu7 / cs0_2 / pl6 emios1[19] / pdi16_viu8 / sin_2 / pl7 emios1[20] / pdi17_viu9 / sout_2 / pl8 emios1[21] / pdi_pclk / sck_2 / pl9 vdde_b vss dculite_tag / emios1[10] / pdi8_viu0 / pk2 dculite_de / emios1[11] / pdi9_viu1 / pk3 dculite_hsync / emios1[12] / pdi10_viu2 / pk4 dculite_vsync / emios1[13] / pdi11_viu3 / pk5 dculite_pclk / emios1[9] / pdi12_viu4 / pk6 tcon8 / dculite_r2 / rxd_2 / pk7 tcon9 / dculite_r3 / txd_2 / pk8 tcon10 / dculite_r4 / i2s_do / pk9 vss vdde_b tck / ph0 tdi / ph1 tdo / ph2 tms / ph3 vdde_b pa13 / dcu_g5 / rsds6m pa12 / dcu_g4 / rsds6p pa11 / dcu_g3 / rsds5m pa10 / dcu_g2 / rsds5p pa9/dcu_g1/sda_2/emios0[19]/rsds4m pa8 / dcu_g0 / scl_2 / emios0[20] / rsds4p pa7 / dcu_r7 / rsds3m pa6 / dcu_r6 / rsds3p vss vdde_b vref_rsds pa5 / dcu_r5 / rsds2m pa4 / dcu_r4 / rsds2p pa3 / dcu_r3 / rsrs1m pa2 / dcu_r2 / rsds1p pa1 / dcu_r1 / scl_1 / emios0[17] / rsds0m pa0 / dcu_r0 / sda_1 / emios0[18] / rsds0p vdde_b vss vdd12 pe7 / m5c1p / ssd5_3 pe6 / m5c1m / ssd5_2 pe5 / m5c0p / ssd5_1 pe4 / m5c0m / ssd5_0 vssm vddm pe3 / m4c1p / ssd4_3 pe2 / m4c1m / ssd4_2 pe1 / m4c0p / ssd4_1 pe0 / m4c0m / ssd4_0 pd15 / m3c1p / ssd3_3 / emios0[15] pd14 / m3c1m / ssd3_2 / emios0[14] pd13 / m3c0p / ssd3_1 / emios0[13] pd12 / m3c0m / ssd3_0 / emios0[12] vssm vddm pd11 / m2c1p / ssd2_3 / emios0[11] pd10 / m2c1m / ssd2_2 / emios0[10] pd9 / m2c0p / ssd2_1 / emios0[9] pd8 / m2c0m / ssd2_0 pd7 / m1c1p / ssd1_3 pd6 / m1c1m / ssd1_2 / emios0[23] pd5 / m1c0p / ssd1_1 / emios0[16] pd4 / m1c0m / ssd1_0 / emios0[8] vssm vddm pd3 / m0c1p / ssd0_3 / emios0[9] pd2 / m0c1m / ssd0_2 / emios1[23] pd1 / m0c0p / ssd0_1 / emios1[16] pd0 / m0c0m / ssd0_0 / emios1[8] vdde_b nmi/pf2 cs2_0 / emios1[10] / rxd_1 / pb12 cs1_0 / emios1[11] / txd_1 / pb13 vdde_b vss vdd12 dcu_tag/emios1[12]/sda_1/pk10 dculite_tag / emios1[13] / scl_1 / pk11 tcon11 / dculite_r5 / i2s_sck/ pm0 dculite_r6 / i2s_fs / pm1 vdde_b vss i2s_fs / emios1[18] / sck_0 / pb9 i2s_do/emios1[19]/sout_0/pb8 i2s_sck / emios1[20] / sin_0 / pb7 emios0[23] / emios0[21] / pdi0_viu2 / pj4 emios0[16] / emios0[20] / pdi1_viu3 / pj5 emios0[15] / emios0[19] / pdi2_viu4 / pj6 emios0[14] / emios0[18] / pdi3_viu5 / pj7 pdi_de/emios0[22]/viu_pclk/pj3 dculite_g6 / emios1[21] / cs0_0 / ph4 ma0 / sck_1 / pb4 fabm / ma1 / sout_1 / pb5 abs[0]/ma2/sin_1/pb6 vdde_b vss vdd12 vss cnrx_1 / an19 / pl0 cntx_1 / an18 / pl1 emios1[22]/cnrx_0/an17/pl2 emios1[23] / cntx_0 / an16 / pl3 xtal32 / an15 / pc15 extal32 / an14 / pc14 cs0_1/ma2/an13/pc13 cs1_1/ma1/an12/pc12 cs2_1/ma0/an11/pc11 i2s_do / an10_mux / pc10 an9 / pc9 an8 / pc8 vdde_a vsse_a vdda vssa an7 / pc7 an6 / pc6 an5 / pc5 an4 / pc4 an3 / pc3 an2 / pc2 an1 / pc1 an0 / pc0 vss vdd12 pf15 / qspi_clk_0 / clkout / mcko pf14 / qspi_io1_0 / mdo3 pf13 / qspi_io0_0 / mdo2 pf12 / qspi_io3_0 / mdo1 pf11 / qspi_io2_0 / mdo0 pf10 / qspi_pcs_0 / evti pg12 / cs0_1 / pdi_de / dculite_b7 vss vdde_b pf9 / scl_0 / cs1_1 / txd_1 pf8 / sda_0 / cs2_1 / rxd_1 pf7 / emios1[15] / scl_1 / dculite_b6 pf6 / qspi_io0_1 / emios1[16] / pdi17_viu9 pf5 / qspi_io1_1 / emios1[15] / pdi16_viu8 pf4 / emios1[14] / sda_b / dculite_b5 pf3 / emios1[21] / mseo2 / dculite_b4 pf1 / emios1[20] / mseo / dculite_b3 pf0 / emios1[19] / evto /dculite_b2 pk1 / qspi_io2_1 / emios1[14] / pdi15_viu7 pk0 / emios1[18] / dculite_g7 vdd12 vss vdde_b pb2 / txd_0 pb3 / rxd_0 pj15 / qspi_io3_1 / emios1[9] / pdi14_viu6 pj14 / qspi_clk_1 / emios1[17] / pdi_pclk pj13 / qspi_pcs_1 / emios1[8] / pdi13_viu5 pj12 / dcu_tag_tcon0 / dculite_g6 pl13/emios1[13]/dculite_g5 pl12/emios1[12]/dculite_g4 pl11/emios1[11]/dculite_g3 pl10/emios1[10]/dculite_g2 pm2 / emios1[17] / dculite_r7/dculite_de/rsdslckm pg11 / dcu_pclk / rsdslckp pg7/ dcu_b7 / rsds11m pg6 / dcu_b6 / rsds11p pg5 / dcu_b5 / rsds10m pg4 / dcu_b4 / rsds10p pg3 / dcu_b3 / rsds9m pg2 / dcu_b2 / rsds9p vref_rsds vdde_b vss vdd12 pg1/dcu_b1/sda_3/emios0[22]/rsds8m pg0 / dcu_b0 / scl_3 / emios0[21] / rsds8p pa15 / dcu_g7 / rsds7m pa14 / dcu_g6 / rsds7p vss
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 26 2.3 416 tepbga package pinout?40 to 105c figure 4 shows the pinout for the 416 tepbga package. figure 4. 416 tepbga pinout 1234567891011121314151617181920212223242526 a ddr_dq[2 6] ddr_dq[2 7] ddr_dq[2 8] ddr_dq[2 9] 30] 31] ddr_ba[0] ddr_ba[1] ddr_ba[2] ddr_addr ess[0] ddr_addr ess[4] ddr_addr ess[6] ddr_addr ess[8] ddr_addr ess[12] pg12 pf14 pf10 pf8 pf5 pf3 pk0 pb3 pj12 pl11 pg7 pg6 a b ddr_dq[2 5] vss ddr_dqs[ 3] ddr_dm[3 ] vss ddr_cas ddr_ras vss ddr_web ddr_addr ess[1] vss ddr_addr ess[7] ddr_addr ess[9] vss ddr_addr ess[15] pf13 vdde pf15 vss pf1 vdde pj15 pl13 vdde vss pg5 b c ddr_dq[2 3]] vdde_dd r vss ddr_dq[2 4] vdde_dd r vss ddr_dram _clk vdde_dd dr vss ddr_addr ess[2] vdde_dd r vss ddr_addr ess[10] vdde_dd r vss pf12 vss pf7 vdde pf0 vss pj14 pl12 pl10 pg3 pg4 c d ddr_dq[1 9] ddr_dq[2 0] ddr_dq[2 1] ddr_dq[2 2] ddr_odt vdd33_d dr ddr_dram _clkb ddr_cke ddr_cs ddr_addr ess[3] ddr_addr ess[5] vdd33_d dr ddr_addr ess[11] ddr_addr ess[13] ddr_addr ess[14] pf11 pf9 pf6 pf4 pk1 pb2 pj13 pm2 vref_rs ds2 pg2 pg1 d e ddr_dq[1 7] vss vdde_dd r ddr_dq[1 8] pg11 vss vdde pg0 e f ddr_dq[1 6] mvtt3 vss vdd33_d dr pa15 pa14 pa13 pa12 f g ddr_dq[1 5] ddr_dqs[ 2] ddr_dm[2 ] ddr_dq[1 4] pa11 pa9 pa8 pa7 g h ddr_dq[1 3] vss vdde_dd r ddr_dq[1 2] pa10 vdde vss va6 h j ddr_dq[1 1] mvtt2 vss mvref pa3 vref_rs ds1 pa5 pa4 j k ddr_dq[9] ddr_dqs[ 1] ddr_dm[1 ] ddr_dq[1 0] vdd12 vss vdd12 vss vdd12 vss vdd12 vss pa2 vss pa1 pa0 k l ddr_dq[8] vss vdde_dd r ddr_dq[7] vss vdd12 vss vdd12 vss vdd12 vss vdd12 pm13 pm12 vdde pj0 l m ddr_dq[5] mvtt1 vss ddr_dq[6] vdd12 vss vss vss vss vss vdd12 vss po7 po6 po5 po4 m n ddr_dq[3] ddr_dqs[ 0] vdde_dd r ddr_dq[4] vss vdd12 vss vss vss vss vss vdd12 po3 vdde po2 po1 n p ddr_dq[1] vss ddr_dm[0 ] ddr_dq[2] vdd12 vss vss vss vss vss vdd12 vss po0 pn15 vss pn14 p r ddr_dq[0] mvtt0 vss vdd33_d dr vss vdd12 vss vss vss vss vss vdd12 pe7 pe6 pn13 pn12 r t pg10 pg9 vdde_dd r pg8 vdd12 vss vdd12 vss vdd12 vss vdd12 vss pe5 pe4 pe3 pe2 t u pj9 pj8 pj2 pj1 vss vdd12 vss vdd12 vss vdd12 vss vdd12 pe1 vssm vddm pe0 u v pb1 vss pj11 pj10 pd15 pd14 pd13 pd12 v w reset pb10 vdde pb0 pd11 vddm vssm pd10 w y vss pm4 pm3 pb11 pd9 pd8 pd7 pd6 y aa xtal vreg_by pass vrc_ctr l vddreg pd5 vssm vddm pd4 aa ab extal pl4 vss vddpll pd3 pd2 pd1 pd0 ab ac vsup_te st pl5 pn0 pk4 pk6 ph0 pf2 pb13 pk11 pn2 pn4 pn8 pb9 pb7 pj7 pb5 mcko mdo6 mdo10 mvo0 pc0 vdda vsseh_a dc pc3 pc1 pc2 ac ad pl6 vdde pn1 vss pk7 ph1 vdde evti mseo vss pn5 pn9 vdde pj4 pj3 vss mseo2 mdo7 vdde mdo1 pc6 vssa vddeh_a dc pc4 pc7 pc5 ad ae pl7 vss pk2 vdde pk8 ph2 vss evto pm0 vdde pn6 pn10 vss pj5 ph4 vdde mdo4 mdo8 vss mdo2 pl1 pl0 pc10 pc11 pc9 pc8 ae af pl8 pl9 pk3 pk5 pk9 ph3 pb12 pk10 pm1 pn3 pn7 pn11 pb8 pj6 pb4 pb6 mdo5 mdo9 mdo11 mdo3 pl3 pl2 pc15 pc14 pc13 pc12 af 123 4567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 27 2.4 signal description the following sections provide signal descriptions and relate d information about the signals? functionality and configuration. 2.4.1 pad configuratio n during reset phases all pads have a fixed configuration under reset. during the power-up phase, all pads are forced to tristate. after power-up phase, all pads are floating with the following exceptions: ? pb[5] (fab) is pull-down. without external strong pull-up the device starts fetching from flash memory. ? reset pad is driven low. this is released only after phase2 reset completion. ?fast (4 - 16 mhz) external oscillator pa ds (extal, xtal) are tristate. ? the following pads are pull-up: ?pb[6] ?ph[0] ?ph[1] ?ph[3] 2.4.2 voltage supply pins voltage supply pins are used to provide power to the device. two dedicated pins are used fo r 1.2 v regulator stabilization. table 3. voltage supply pin descriptions supply pin function pin number 176 lqfp 208 lqfp 416 tepbga v dd12 1 1.2 v core supply (1.08 v - 1.32 v) 23, 50, 67, 110, 138, 175 23, 58, 79, 136, 162, 186, 207 k10,k12,k14,k16,l 11,l13,l15,l17,m1 0,m16,n11,n17,p1 0,p16,r11,r17,t10 ,t12,t14,t16,u11, u13,u15,u17
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 28 v ss 1.2 v ground 7, 18, 36, 49, 66, 68, 111, 123, 133, 139, 154, 167, 176 7, 18, 38, 47, 57, 64, 78, 80, 137, 147, 157, 163, 185, 199, 208 ab3,ad10,ad16,a d4,ae13,ae19,ae2 ,ae7,b11,b14,b19, b2,b25,b5,b8,c12, c15,c17,c21,c3,c 6,c9,e2,e24,f3,h2 ,h25,j3,k11,k13,k 15,k17,k24,l10,l1 2,l14,l16,l2,m11, m12,m13,m14,m15, m17,m3,n10,n12,n 13,n14,n15,n16,p 11,p12,p13,p14,p1 5,p17,p2,p25,r10, r12,r13,r14,r15, r16,r3,t11,t13,t1 5,t17,u10,u12,u14 ,u16,v2,y1 vdd12 ground and vddpll ground (vsspll) 24 24 ? v dde_b 3.3 v i/o supply. this supply is shared with internal flash, 16 mhz irc oscillator and 4?16mhz crystal oscillator. 6, 19, 37, 48, 65, 89, 112, 122, 132, 140, 166 6, 19, 37, 48, 56, 63, 77, 105, 138, 146, 156, 164, 184, 198 ad13,ad19,ad2,a d7,ae10,ae16,ae4 ,b17,b21,b24,c19, e25,h24,l25,n24, w3 v dda 2 3.3 v/5 v reference voltage and analog supply for a/d converter. this supply is shared with the sxosc. 79 95 ac22 v ssa reference ground and analog ground for a/d converter 80 96 ad22 v ddr voltage regulator vreg supply 20 20 aa4 v ssr voltage regulator ground 21 21 ? v dde_a 2 3.3 v/5 v i/o supply. this supply is shared with the sxosc. 77 93 ad23 v sse_a 3.3 v/5 v i/o supply ground 78 94 ac23 v ddm stepper motor 3.3 v/5 v pad supply. ssd shares this supply. 94, 104 110, 120, 130 u25,w24,aa25 v ssm stepper motor ground 95, 105 111, 121, 131 u24,w24,aa24 v ddpll 1.2 v pll supply 25 25 ab4 v sup_test 3 9 v - 12 v flash test analog write signal 22 22 ac1 v dd_dr 1.8v, 2.5v, and 3.3v ddr sdram supply ? ? c2,c5,c8,c11,c14, e3,h3,l3,n3,t3 v dd33_dr functional supply for sdram pads (where available must be >= vdd_dr) ? ? d6, d12, f4, r4 table 3. voltage supply pin descriptions (continued) supply pin function pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 29 2.4.3 pad types the pads available for system pins and functional port pins are described in: ? the port pin summary in table 1 ; ? the pad type descriptions in table 3-6 ; ? section 43.5.3.8, ?pad configuration registers (pcr0?pcr184) and section 43.5.3.9, ?pad configuration registers (pcr185?pcr281) ; ? the device data sheet. 2.4.4 system pins the system pins are listed in table 4 . 1 decoupling capacitors must be connect ed between these pins and the nearest v ss pin. 2 vdda must be at the same voltage as vdde_a. 3 this signal needs to be connected to ground during normal operation. table 4. system pin descriptions system pin function i/o direction pad type reset configuration 1 pin number 176 lqfp 208 lqfp 416 tepbga reset bidirectional reset with schmitt-trigger characteristics and noise filter. i/o m input, weak pull up 30 30 w1 extal analog input to the oscillator amplifier circuit. input for the clock generator in bypass mode. i x ? 27 27 ab1 xtal analog output of the oscillator amplifier circuit. needs to be grounded if oscillator bypass mode is used. o x ? 28 28 aa1 extal32 analog input of the 32khz oscillator amplifier circuit. os ? 70 86 af24 xtal32 analog output of the 32 khz oscillator amplifier circuit. input for the clock generator in bypass mode. is ? 69 85 af23 nmi non-maskable interrupt i/o s input, none 45 53 ac7 vrc_ctrl voltage regulator external npn ballast base control pin analo g ? 29 29 aa3 vref_ rsds 2 rsds interface reference voltage analo g ? ? 145, 165 j24,d24 vreg_ bypass 3 pin used for factory testing i ? ? 26 26 aa2
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 30 2.4.5 nexus pins on the 176 lqfp and the 208 lqfp package options a reduced set of nexus pins are optionally available, multiplexed with gpio pins. on the 416 tepbga package option all nexu s pins are dedicated to nexus only. 1 reset configuration is given as i/o direction an d pull direction (for example, ?input, pullup?). 2 although this signal is not a supply for rsds pads, it needs to be terminated in an external capacitor with a value of 47 pf. 3 vreg_bypass should be pulled down externally. table 5. nexus pins system pin function pad type pcr pin number 1 176 lqfp 208 lqfp 416 tepbga evti nexus event in m pcr[80] 169 201 a17 evto nexus event out m pcr[70] 157 189 c20 mcko nexus msg clock out f pcr[85] 174 206 b18 mseo[0] nexus msg start/end out m pcr[71] 158 190 b20 mseo[2] nexus msg start/end out m pcr[73] 159 191 a20 mdo[0] nexus msg data out m pcr[81] 170 202 d16 mdo[1] nexus msg data out m pcr[82] 171 203 c16 mdo[2] nexus msg data out m pcr[83] 172 204 b16 mdo[3] nexus msg data out m pcr[84] 173 205 a16 evti nexus event in m pcr[197] n/a n/a ad8 evto nexus event out m pcr[198] n/a n/a ae8 mcko nexus msg clock out f pcr[200] n/a n/a ac17 mseo[0] nexus msg start/end out m pcr[199] n/a n/a ad9 mseo[2] nexus msg start/end out m pcr[201] n/a n/a ad17 mdo[0] nexus msg data out m pcr[185] n/a n/a ac20 mdo[1] nexus msg data out m pcr[186] n/a n/a ad20 mdo[2] nexus msg data out m pcr[187] n/a n/a ae20 mdo[3] nexus msg data out m pcr[188] n/a n/a af20 mdo[4] nexus msg data out m pcr[189] n/a n/a ae17 mdo[5] nexus msg data out m pcr[190] n/a n/a af17 mdo[6] nexus msg data out m pcr[191] n/a n/a ac18 mdo[7] nexus msg data out m pcr[192] n/a n/a ad18
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 31 2.4.6 dram interface the dram interface pins are listed in table 6 . mdo[8] nexus msg data out m pcr[193] n/a n/a ae18 mdo[9] nexus msg data out m pcr[194] n/a n/a af18 mdo[10] nexus msg data out m pcr[195] n/a n/a ac19 mdo[11] nexus msg data out m pcr[196] n/a n/a af19 1 on the 176 lqfp and 208 lqfp package options the nexus pi ns are multiplexed with other gpio. on the 416 tepbga package, there are additional dedicated nexus pins. table 6. dram interface pin summary port pin 1 function i/o direction pad type pcr reset config 2 pin number 416 tepbga dram data bus ddr_dq[31] dram data bus [31] i/o ddr pcr[237] none, none a6 ddr_dq[30] dram data bus [30] i/o ddr pcr[238] none, none a5 ddr_dq[29] dram data bus [29] i/o ddr pcr[239] none, none a4 ddr_dq[28] dram data bus [28] i/o ddr pcr[240] none, none a3 ddr_dq[27] dram data bus [27] i/o ddr pcr[241] none, none a2 ddr_dq[26] dram data bus [26] i/o ddr pcr[242] none, none a1 ddr_dq[25] dram data bus [25] i/o ddr pcr[243] none, none b1 ddr_dq[24] dram data bus [24] i/o ddr pcr[244] none, none c4 ddr_dq[23] dram data bus [23] i/o ddr pcr[245] none, none c1 ddr_dq[22] dram data bus [22] i/o ddr pcr[246] none, none d4 ddr_dq[21] dram data bus [21] i/o ddr pcr[247] none, none d3 ddr_dq[20] dram data bus [20] i/o ddr pcr[248] none, none d2 ddr_dq[19] dram data bus [19] i/o ddr pcr[249] none, none d1 ddr_dq[18] dram data bus [18] i/o ddr pcr[250] none, none e4 ddr_dq[17] dram data bus [17] i/o ddr pcr[251] none, none e1 ddr_dq[16] dram data bus [16] i/o ddr pcr[252] none, none f1 ddr_dq[15] dram data bus [15] i/o ddr pcr[253] none, none g1 ddr_dq[14] dram data bus [14] i/o ddr pcr[254] none, none g4 ddr_dq[13] dram data bus [13] i/o ddr pcr[255] none, none h1 ddr_dq[12] dram data bus [12] i/o ddr pcr[256] none, none h4 table 5. nexus pins (continued) system pin function pad type pcr pin number 1 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 32 ddr_dq[11] dram data bus [11] i/o ddr pcr[257] none, none j1 ddr_dq[10] dram data bus [10] i/o ddr pcr[258] none, none k4 ddr_dq[9] dram data bus [9] i/o ddr pcr[259] none, none k1 ddr_dq[8] dram data bus [8] i/o ddr pcr[260] none, none l1 ddr_dq[7] dram data bus [7] i/o ddr pcr[261] none, none l4 ddr_dq[6] dram data bus [6] i/o ddr pcr[262] none, none m4 ddr_dq[5] dram data bus [5] i/o ddr pcr[263] none, none m1 ddr_dq[4] dram data bus [4] i/o ddr pcr[264] none, none n4 ddr_dq[3] dram data bus [3] i/o ddr pcr[265] none, none n1 ddr_dq[2] dram data bus [2] i/o ddr pcr[266] none, none p4 ddr_dq[1] dram data bus [1] i/o ddr pcr[267] none, none p1 ddr_dq[0] dram data bus [0] i/o ddr pcr[268] none, none r1 dram data strobes ddr_dqs[3] dram data strobe [3] i/o ddr pcr[232] none, none b3 ddr_dqs[2] dram data strobe [2] i/o ddr pcr[231] none, none g2 ddr_dqs[1] dram data strobe [1] i/o ddr pcr[230] none, none k2 ddr_dqs[0] dram data strobe [0] i/o ddr pcr[229] none, none n2 dram data enables ddr_dm[3] dram data enable [3] output ddr pcr[236] output, none b4 ddr_dm[2] dram data enable [2] output ddr pcr[235] output, none g3 ddr_dm[1] dram data enable [1] output ddr pcr[234] output, none k3 ddr_dm[0] dram data enable [0] output ddr pcr[233] output, none p3 dram address ddr_a[15] dram address [15] output ddr pcr[217] output, none b15 ddr_a[14] dram address [14] output ddr pcr[216] output, none d15 ddr_a[13] dram address [13] output ddr pcr[215] output, none d14 ddr_a[12] dram address [12] output ddr pcr[214] output, none a14 ddr_a[11] dram address [11] output ddr pcr[213] output, none d13 table 6. dram interface pin summary (continued) port pin 1 function i/o direction pad type pcr reset config 2 pin number 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 33 ddr_a[10] dram address [10] output ddr pcr[212] output, none c13 ddr_a[9] dram address [9] output ddr pcr[211] output, none b13 ddr_a[8] dram address [8] output ddr pcr[210] output, none a13 ddr_a[7] dram address [7] output ddr pcr[209] output, none b12 ddr_a[6] dram address [6] output ddr pcr[208] output, none a12 ddr_a[5] dram address [5] output ddr pcr[207] output, none d11 ddr_a[4] dram address [4] output ddr pcr[206] output, none a11 ddr_a[3] dram address [3] output ddr pcr[205] output, none d10 ddr_a[2] dram address [2] output ddr pcr[204] output, none c10 ddr_a[1] dram address [1] output ddr pcr[203] output, none b10 ddr_a[0] dram address [0] output ddr pcr[202] output, none a10 dram bank address ddr_ba[2] dram bank address[2] output ddr pcr[220] output, none a9 ddr_ba[1] dram bank address[1] output ddr pcr[219] output, none a8 ddr_ba[0] dram bank address[0] output ddr pcr[218] output, none a7 dram control ddr_cas column address strobe output ddr pcr[221] output, none b6 ddr_ras row address strobe output ddr pcr[227] output, none b7 ddr_web write enable output ddr pcr[228] output, none b9 ddr_odt dram on-die termination output ddr pcr[226] output, pull down d5 ddr_clk dram clock output ddr pcr[225] output, none c7 table 6. dram interface pin summary (continued) port pin 1 function i/o direction pad type pcr reset config 2 pin number 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 34 2.4.7 viu muxing the dcu3, dculite and viu2 modules share th e same pins for input video. it is, however, possibile to feed independent video streams to viu2 and dcu3 (operating in narrow mode). figure 5 explains the pin sharing arrangement. figure 5. viu2, dcu3, and dculite pin sharing viu input data selection is done based on select bit (b it 0) of miscellaneous control register (0xc3fe0340). ? viu pix data: viu[9:0] ? select bit 1?b0: pdi[7:0],hsync,vsync ? select bit 1?b1: pdi[17:8] ddr_clkb dram clock bar output ddr na output, none d7 ddr_ck dram clock enable output ddr pcr[222] output, pull down d8 ddr_cs dram chip select output ddr pcr[223] output, none d9 mvref ddr reference voltage input ? na ? j4 mvtt dram termination voltage input ? na ? f2,j2,m2,r2 1 these port pins are disabled and unpowered on packages where the dram interface is not bonded out. 2 reset configuration is given as i/o direction an d pull direction (for example, ?input, pullup?). table 6. dram interface pin summary (continued) port pin 1 function i/o direction pad type pcr reset config 2 pin number 416 tepbga viu2 dcu3 dculite pdi pdi viu[9:0] de pdi_pclk vsync hsync data[17:0] viu_pclk data[17:8] data[7:0] xbar direct feed of pdi interface to dcu3 or dculite rgb565 rgb888 8-bit mono yuv422
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 35 2.4.8 sgm muxing the sgm shares pins between the pwm output signals and the i2s bus signals as shown in the ?port pin summary? table. when the pwm function is enabled in the sgm (sgmctl[pwme]) th e pwm (pwmo, pwmoa) signals are available. when the pwm function is disabled the i2s bus signals (i2s_do, i2s_ sck) are available. 2.4.9 rsds special function muxing ports pa[0:15], pg[0:7], pg[11] and pm[2] have the rsds si gnalling option as a special func tion. the siul allocates pad control registers to these functions (pcr [270:282]), but because these pads share a common pin with the normal gpio pins they do not operate in the same way as th e normal gpio ports. pg[11] in particular has a special configuration separate from the other pads. the special-function pads are output-only, and the associated pcr[obe] bit is controlled by the tcon_ctrl1 register (tcon_bypass and rsds_mode bits). howeve r, the alternate fu nction selection is taken from the associated normal gpio pad. this allows selection of the dcu3 fu nction as the alternate function of the pad and then the tcon module to select if the output style is tcon/rsds or digital rgb format. therefore, when the tcon bypass is active (bypass disabled with or without rsds active), it is important not to configure the normal gpio ports for output operation with a non-dcu3 alternate function on ports pa[0:15] and pg[0:7]. for pg[11], the pcr[282] obe bit is fully controlled by the tcon module and will become an output whenever the dcu3 alternate option is selected. ther efore, only select the dcu3 fu nction on this pin when ready to configure it as a clock for a tft panel.
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 36 2.4.10 functional ports the functional port pins are listed in table 7 . the following pad types are available for system pins and functional port pins: ? s ? slow (pad_ssr, pad_ssr_hv) ? m ? medium (pad_msr, pad_msr_hv) ? f ? fast (pad_fc) ? j ? input/output with analog f eatures (pad_tgate, pad_tgate_hv) ? analog ? input only with analog features (pad_ae, pad_ae_hv) ? smd ? stepper motor detector ? ddr ? ddr pads ? rsds ? rsds pads table 7. port pin summary port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga port a pa[0] pcr[0] option 0 option 1 option 2 option 3 gpio[0] dcu_r0 sda_1 emios0[18] rsds0p siul dcu3 i 2 c_1 pwm/timer i/o m / rsds none, none 116 139 k26 pa[1] pcr[1] option 0 option 1 option 2 option 3 gpio[1] dcu_r1 scl_1 emios0[17] rsds0m siul dcu3 i 2 c_1 pwm/timer i/o m / rsds none, none 117 140 k25 pa[2] pcr[2] option 0 option 1 option 2 option 3 gpio[2] dcu_r2 ? ? rsds1p siul dcu3 ? ? i/o m / rsds none, none 118 141 k23 pa[3] pcr[3] option 0 option 1 option 2 option 3 gpio[3] dcu_r3 ? ? rsds1m siul dcu3 ? ? i/o m / rsds none, none 119 142 j23 pa[4] pcr[4] option 0 option 1 option 2 option 3 gpio[4] dcu_r4 ? ? rsds2p siul dcu3 ? ? i/o m / rsds none, none 120 143 j26
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 37 pa[5] pcr[5] option 0 option 1 option 2 option 3 gpio[5] dcu_r5 ? ? rsds2m siul dcu3 ? ? i/o m / rsds none, none 121 144 j25 pa[6] pcr[6] option 0 option 1 option 2 option 3 gpio[6] dcu_r6 ? ? rsds3p siul dcu3 ? ? i/o m / rsds none, none 124 148 h26 pa[7] pcr[7] option 0 option 1 option 2 option 3 gpio[7] dcu_r7 ? ? rsds3m siul dcu3 ? ? i/o m / rsds none, none 125 149 g26 pa[8] pcr[8] option 0 option 1 option 2 option 3 gpio[8] dcu_g0 scl_2 emios0[20] rsds4p siul dcu3 i 2 c_2 pwm/timer i/o m / rsds none, none 126 150 g25 pa[9] pcr[9] option 0 option 1 option 2 option 3 gpio[9] dcu_g1 sda_2 emios0[19] rsds4m siul dcu3 i 2 c_2 pwm/timer i/o m / rsds none, none 127 151 g24 pa[10] pcr[10] option 0 option 1 option 2 option 3 gpio[10] dcu_g2 ? ? rsds5p siul dcu3 ? ? i/o m / rsds none, none 128 152 h23 pa[11] pcr[11] option 0 option 1 option 2 option 3 gpio[11] dcu_g3 ? ? rsds5m siul dcu3 ? ? i/o m / rsds none, none 129 153 g23 pa[12] pcr[12] option 0 option 1 option 2 option 3 gpio[12] dcu_g4 ? ? rsds6p siul dcu3 ? ? i/o m / rsds none, none 130 154 f26 pa[13] pcr[13] option 0 option 1 option 2 option 3 gpio[13] dcu_g5 ? ? rsds6m siul dcu3 ? ? i/o m / rsds none, none 131 155 f25 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 38 pa[14] pcr[14] option 0 option 1 option 2 option 3 gpio[14] dcu_g6 ? ? rsds7p siul dcu3 ? ? i/o m / rsds none, none 134 158 f24 pa[15] pcr[15] option 0 option 1 option 2 option 3 gpio[15] dcu_g7 ? ? rsds7m siul dcu3 ? ? i/o m / rsds none, none 135 159 f23 port b pb[0] pcr[16] option 0 option 1 option 2 option 3 gpio[16] cantx_0 txd_0 ? ?siul flexcan_0 linflex_0 ? i/o s none, none 13 13 w4 pb[1] pcr[17] option 0 option 1 option 2 option 3 gpio[17] canrx_0 rxd_0 ? ?siul flexcan_0 linflex_0 ? i/o s none, none 12 12 v1 pb[2] pcr[18] option 0 option 1 option 2 option 3 gpio[18] txd_0 ? ? ?siul linflex_0 ? ? i/o s none, none 153 183 d21 pb[3] pcr[19] option 0 option 1 option 2 option 3 gpio[19] rxd_0 ? ? ?siul linflex_0 ? ? i/o s none, none 152 182 a22 pb[4] pcr[20] option 0 option 1 option 2 option 3 gpio[20] sck_1 ma0 ? ?siul dspi_1 adc ? i/o s none, none 62 74 af15 pb[5] pcr[21] option 0 option 1 option 2 option 3 gpio[21] sout_1 ma1 fabm ?siul dspi_1 adc control i/o s input, pull- down 63 75 ac16 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 39 pb[6] pcr[22] option 0 option 1 option 2 option 3 gpio[22] sin_1 ma2 abs[0] ?siul dspi_1 adc control i/o s input, pull- up 64 76 af16 pb[7] pcr[23] option 0 option 1 option 2 option 3 gpio[23] sin_0 emios1[20] i2s_sck/pwmoa ?siul dspi_0 pwm/timer sgm i/o s none, none 55 67 ac14 pb[8] pcr[24] option 0 option 1 option 2 option 3 gpio[24] sout_0 emios1[19] i2s_do/pwmo ?siul dspi_0 pwm/timer sgm i/o s none, none 54 66 af13 pb[9] pcr[25] option 0 option 1 option 2 option 3 gpio[25] sck_0 emios1[18] i2s_fs ?siul dspi_0 pwm/timer sgm i/o m none, none 53 65 ac13 pb[10] pcr[26] option 0 option 1 option 2 option 3 gpio[26] canrx_1 i2s_do/pwmo ? ?siul flexcan_1 sgm ? i/o s none, none 14 14 w2 pb[11] pcr[27] option 0 option 1 option 2 option 3 gpio[27] cantx_1 sgm_mclk ? ?siul flexcan_1 sgm ? i/o s none, none 15 15 y4 pb[12] pcr[28] option 0 option 1 option 2 option 3 gpio[28] rxd_1 emios1[10] cs2_0 ?siul linflex_1 pwm/timer dspi_0 i/o s none, none 46 54 af7 pb[13] pcr[29] option 0 option 1 option 2 option 3 gpio[29] txd_1 emios1[11] cs1_0 ?siul linflex_1 pwm/timer dspi_0 i/o s none, none 47 55 ac8 pb[14] ? ? reserved ? ? ? ? ? ? ? ? pb[15] ? ? reserved ? ? ? ? ? ? ? ? table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 40 port c pc[0] pcr[30] option 0 option 1 option 2 option 3 gpio[30] ? ? ? ans[0] siul ? ? ? i/o j none, none 88 104 ac21 pc[1] pcr[31] option 0 option 1 option 2 option 3 gpio[31] ? ? ? ans[1] siul ? ? ? i/o j none, none 87 103 ac25 pc[2] pcr[32] option 0 option 1 option 2 option 3 gpio[32] ? ? ? ans[2] siul ? ? ? i/o j none, none 86 102 ac26 pc[3] pcr[33] option 0 option 1 option 2 option 3 gpio[33] ? ? ? ans[3] siul ? ? ? i/o j none, none 85 101 ac24 pc[4] pcr[34] option 0 option 1 option 2 option 3 gpio[34] ? ? ? ans[4] siul ? ? ? i/o j none, none 84 100 ad24 pc[5] pcr[35] option 0 option 1 option 2 option 3 gpio[35] ? ? ? ans[5] siul ? ? ? i/o j none, none 83 99 ad26 pc[6] pcr[36] option 0 option 1 option 2 option 3 gpio[36] ? ? ? ans[6] siul ? ? ? i/o j none, none 82 98 ad21 pc[7] pcr[37] option 0 option 1 option 2 option 3 gpio[37] ? ? ? ans[7] siul ? ? ? i/o j none, none 81 97 ad25 pc[8] pcr[38] option 0 option 1 option 2 option 3 gpio[38] ? ? ? ans[8] siul ? ? ? i/o j none, none 76 92 ae26 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 41 pc[9] pcr[39] option 0 option 1 option 2 option 3 gpio[39] ? ? ? ans[9] siul ? ? ? i/o j none, none 75 91 ae25 pc[10] pcr[40] option 0 option 1 option 2 option 3 gpio[40] ? i2s_do/pwmo ? ans[10] siul ? sgm ? i/o j none, none 74 90 ae23 pc[11] pcr[41] option 0 option 1 option 2 option 3 gpio[41] ? ma0 cs2_1 ans[11] siul ? adc dspi_1 i/o j none, none 73 89 ae24 pc[12] pcr[42] option 0 option 1 option 2 option 3 gpio[42] ? ma1 cs1_1 ans[12] siul ? adc dspi_1 i/o j none, none 72 88 af26 pc[13] pcr[43] option 0 option 1 option 2 option 3 gpio[43] ? ma2 cs0_1 ans[13] siul ? adc dspi_1 i/o j none, none 71 87 af25 pc[14] pcr[44] option 0 option 1 option 2 option 3 gpio[44] ? ? ? ans[14] extal32 siul ? ? ? i/o j none, none 70 86 af24 pc[15] pcr[45] option 0 option 1 option 2 option 3 gpio[45] ? ? ? ans[15] xtal32 siul ? ? ? i/o j none, none 69 85 af23 port d pd[0] pcr[46] option 0 option 1 option 2 option 3 gpio[46] m0c0m ssd0_0 emios1[8] ?siul smd ssd pwm/timer i/o smd none, none 90 106 ab26 pd[1] pcr[47] option 0 option 1 option 2 option 3 gpio[47] m0c0p ssd0_1 emios1[16] ?siul smd ssd pwm/timer i/o smd none, none 91 107 ab25 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 42 pd[2] pcr[48] option 0 option 1 option 2 option 3 gpio[48] m0c1m ssd0_2 emios1[23] ?siul smd ssd pwm/timer i/o smd none, none 92 108 ab24 pd[3] pcr[49] option 0 option 1 option 2 option 3 gpio[49] m0c1p ssd0_3 emios0[9] ?siul smd ssd pwm/timer i/o smd none, none 93 109 ab23 pd[4] pcr[50] option 0 option 1 option 2 option 3 gpio[50] m1c0m ssd1_0 emios0[8] ?siul smd ssd pwm/timer i/o smd none, none 96 112 aa26 pd[5] pcr[51] option 0 option 1 option 2 option 3 gpio[51] m1c0p ssd1_1 emios0[16] ?siul smd ssd pwm/timer i/o smd none, none 97 113 aa23 pd[6] pcr[52] option 0 option 1 option 2 option 3 gpio[52] m1c1m ssd1_2 emios0[23] ?siul smd ssd pwm/timer i/o smd none, none 98 114 y26 pd[7] pcr[53] option 0 option 1 option 2 option 3 gpio[53] m1c1p ssd1_3 ? ?siul smd ssd ? i/o smd none, none 99 115 y25 pd[8] pcr[54] option 0 option 1 option 2 option 3 gpio[54] m2c0m ssd2_0 ? ?siul smd ssd ? i/o smd none, none 100 116 y24 pd[9] pcr[55] option 0 option 1 option 2 option 3 gpio[55] m2c0p ssd2_1 emios0[9] ?siul smd ssd pwm/timer i/o smd none, none 101 117 y23 pd[10] pcr[56] option 0 option 1 option 2 option 3 gpio[56] m2c1m ssd2_2 emios0[10] ?siul smd ssd pwm/timer i/o smd none, none 102 118 w26 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 43 pd[11] pcr[57] option 0 option 1 option 2 option 3 gpio[57] m2c1p ssd2_3 emios0[11] ?siul smd ssd pwm/timer i/o smd none, none 103 119 w23 pd[12] pcr[58] option 0 option 1 option 2 option 3 gpio[58] m3c0m ssd3_0 emios0[12] ?siul smd ssd pwm/timer i/o smd none, none 106 122 v26 pd[13] pcr[59] option 0 option 1 option 2 option 3 gpio[59] m3c0p ssd3_1 emios0[13] ?siul smd ssd pwm/timer i/o smd none, none 107 123 v25 pd[14] pcr[60] option 0 option 1 option 2 option 3 gpio[60] m3c1m ssd3_2 emios0[14] ?siul smd ssd pwm/timer i/o smd none, none 108 124 v24 pd[15] pcr[61] option 0 option 1 option 2 option 3 gpio[61] m3c1p ssd3_3 emios0[15] ?siul smd ssd pwm/timer i/o smd none, none 109 125 v23 port e pe[0] pcr[62] option 0 option 1 option 2 option 3 gpio[62] m4c0m ssd4_0 ? ?siul smd ssd ? i/o smd none, none ? 126 u26 pe[1] pcr[63] option 0 option 1 option 2 option 3 gpio[63] m4c0p ssd4_1 ? ?siul smd ssd ? i/o smd none, none ? 127 u23 pe[2] pcr[64] option 0 option 1 option 2 option 3 gpio[64] m4c1m ssd4_2 ? ?siul smd ssd ? i/o smd none, none ? 128 t26 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 44 pe[3] pcr[65] option 0 option 1 option 2 option 3 gpio[65] m4c1p ssd4_3 ? ?siul smd ssd ? i/o smd none, none ? 129 t25 pe[4] pcr[66] option 0 option 1 option 2 option 3 gpio[66] m5c0m ssd5_0 ? ?siul smd ssd ? i/o smd none, none ? 132 t24 pe[5] pcr[67] option 0 option 1 option 2 option 3 gpio[67] m5c0p ssd5_1 ? ?siul smd ssd ? i/o smd none, none ? 133 t23 pe[6] pcr[68] option 0 option 1 option 2 option 3 gpio[68] m5c1m ssd5_2 ? ?siul smd ssd ? i/o smd none, none ? 134 r24 pe[7] pcr[69] option 0 option 1 option 2 option 3 gpio[69] m5c1p ssd5_3 ? ?siul smd ssd ? i/o smd none, none ? 135 r23 port f pf[0] pcr[70] option 0 option 1 option 2 option 3 gpio[70] emios1[19] evto dculite_b2 ?siul pwm/timer nexus dculite i/o m none, none 157 189 c20 pf[1] pcr[71] option 0 option 1 option 2 option 3 gpio[71] emios1[20] mseo dculite_b3 ?siul pwm/timer nexus dculite i/o m none, none 158 190 b20 pf[2] pcr[72] option 0 option 1 option 2 option 3 gpio[72] nmi ? ? ?siul nmi ? ? i/o s none, none 45 53 ac7 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 45 pf[3] pcr[73] option 0 option 1 option 2 option 3 gpio[73] emios1[21] mseo dculite_b4 ?siul pwm/timer nexus dculite i/o m none, none 159 191 a20 pf[4] pcr[74] option 0 option 1 option 2 option 3 gpio[74] emios1[14] sda_1 dculite_b5 ?siul pwm/timer i 2 c_1 dculite i/o m none, none 160 192 d19 pf[5] pcr[75] option 0 option 1 option 2 option 3 gpio[75] quadspi_io1_b emios1[15] viu8_pdi16 ?siul quadspi pwm/timer viu2/pdi i/o m none, none 161 193 a19 pf[6] pcr[76] option 0 option 1 option 2 option 3 gpio[76] quadspi_io0_b emios1[16] viu9_pdi17 ?siul quadspi pwm/timer viu2/pdi i/o m none, none 162 194 d18 pf[7] pcr[77] option 0 option 1 option 2 option 3 gpio[77] emios1[15] scl_1 dculite_b6 ?siul pwm/timer i 2 c_1 dculite i/o m none, none 163 195 c18 pf[8] pcr[78] option 0 option 1 option 2 option 3 gpio[78] sda_0 cs2_1 rxd_1 ?siul i 2 c_0 dspi_1 linflex_1 i/o s none, none 164 196 a18 pf[9] pcr[79] option 0 option 1 option 2 option 3 gpio[79] scl_0 cs1_1 txd_1 ?siul i 2 c_0 dspi_1 linflex_1 i/o s none, none 165 197 d17 pf[10] pcr[80] option 0 option 1 option 2 option 3 gpio[80] quadspi_pcs_a ? evti ?siul quadspi ? nexus i/o m none, none 169 201 a17 pf[11] pcr[81] option 0 option 1 option 2 option 3 gpio[81] quadspi_io2_a ? mdo0 ?siul quadspi ? nexus i/o m none, none 170 202 d16 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 46 pf[12] pcr[82] option 0 option 1 option 2 option 3 gpio[82] quadspi_io3_a ? mdo1 ?siul quadspi ? nexus i/o m none, none 171 203 c16 pf[13] pcr[83] option 0 option 1 option 2 option 3 gpio[83] quadspi_io0_a ? mdo2 ?siul quadspi ? nexus i/o m none, none 172 204 b16 pf[14] pcr[84] option 0 option 1 option 2 option 3 gpio[84] quadspi_io1_a ? mdo3 ?siul quadspi ? nexus i/o m none, none 173 205 a16 pf[15] pcr[85] option 0 option 1 option 2 option 3 gpio[85] quadspi_clk_a clkout mcko ?siul quadspi control nexus i/o f none, none 174 206 b18 port g pg[0] pcr[86] option 0 option 1 option 2 option 3 gpio[86] dcu_b0 scl_3 emios0[21] rsds8p siul dcu3 i 2 c_3 pwm/timer i/o m none, none 136 160 e26 pg[1] pcr[87] option 0 option 1 option 2 option 3 gpio[87] dcu_b1 sda_3 emios0[22] rsds8m siul dcu3 i 2 c_3 pwm/timer i/o m none, none 137 161 d26 pg[2] pcr[88] option 0 option 1 option 2 option 3 gpio[88] dcu_b2 ? ? rsds9p siul dcu3 ? ? i/o m none, none 141 166 d25 pg[3] pcr[89] option 0 option 1 option 2 option 3 gpio[89] dcu_b3 ? ? rsds9m siul dcu3 ? ? i/o m none, none 142 167 c25 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 47 pg[4] pcr[90] option 0 option 1 option 2 option 3 gpio[90] dcu_b4 ? ? rsds10p siul dcu3 ? ? i/o m none, none 143 168 c26 pg[5] pcr[91] option 0 option 1 option 2 option 3 gpio[91] dcu_b5 ? ? rsds10m siul dcu3 ? ? i/o m none, none 144 169 b26 pg[6] pcr[92] option 0 option 1 option 2 option 3 gpio[92] dcu_b6 ? ? rsds11p siul dcu3 ? ? i/o m none, none 145 170 a26 pg[7] pcr[93] option 0 option 1 option 2 option 3 gpio[93] dcu_b7 ? ? rsds11m siul dcu3 ? ? i/o m none, none 146 171 a25 pg[8] pcr[94] option 0 option 1 option 2 option 3 gpio[94] dcu_vsync ? ? ?siul dcu3 ? ? i/o m none, none 11 t4 pg[9] pcr[95] option 0 option 1 option 2 option 3 gpio[95] dcu_hsync ? ? ?siul dcu3 ? ? i/o m none, none 22 t2 pg[10] pcr[96] option 0 option 1 option 2 option 3 gpio[96] dcu_de ? ? ?siul dcu3 ? ? i/o m none, none 33 t1 pg[11] pcr[97] option 0 option 1 option 2 option 3 gpio[97] dcu_pclk ? ? rsdsclkp siul dcu3 ? ? i/o f none, none 147 172 e23 pg[12] pcr[98] option 0 option 1 option 2 option 3 gpio[98] cs0_1 pdi_de dculite_b7 ?siul dspi_1 pdi dculite i/o m none, none 168 200 a15 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 48 pg[13] ? ? reserved ? ? ? ? ? ? ? ? pg[14] ? ? reserved ? ? ? ? ? ? ? ? pg[15] ? ? reserved ? ? ? ? ? ? ? ? port h ph[0] 6 pcr[99] option 0 option 1 option 2 option 3 gpio[99] tck ? ? ?siul jtag ? ? i/o s input, pull up 41 49 ac6 ph[1] 6 pcr[100] option 0 option 1 option 2 option 3 gpio[100] tdi ? ? ?siul jtag ? ? i/o s input, pull up 42 50 ad6 ph[2] 6 pcr[101] option 0 option 1 option 2 option 3 gpio[101] tdo ? ? ?siul jtag ? ? i/o m output, none 43 51 ae6 ph[3] 6 pcr[102] option 0 option 1 option 2 option 3 gpio[102] tms ? ? ?siul jtag ? ? i/o s input, pull up 44 52 af6 ph[4] pcr[103] option 0 option 1 option 2 option 3 gpio[103] cs0_0 emios1[21] dculite_g6 ?siul dspi_0 pwm/timer dculite i/o m none, none 61 73 ae15 ph[5] pcr[104] option 0 option 1 option 2 option 3 gpio[104] viu7_pdi15 i2s_fs emios1[8] ?siul viu2/pdi sgm pwm/timer i/o s none, none 38 ? ? ph[6] ? ? reserved ? ? ? ? ? ? ? ? ph[7] ? ? reserved ? ? ? ? ? ? ? ? ph[8] ? ? reserved ? ? ? ? ? ? ? ? ph[9] ? ? reserved ? ? ? ? ? ? ? ? ph[10] ? ? reserved ? ? ? ? ? ? ? ? table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 49 ph[11] ? ? reserved ? ? ? ? ? ? ? ? ph[12] ? ? reserved ? ? ? ? ? ? ? ? ph[13] ? ? reserved ? ? ? ? ? ? ? ? ph[14] ? ? reserved ? ? ? ? ? ? ? ? ph[15] ? ? reserved ? ? ? ? ? ? ? ? port j pj[0] pcr[105] option 0 option 1 option 2 option 3 gpio[105] dculite_b6 ? i2s_do / pwmo ?siul dculite ? sgm i/o m none, none ? ? l26 pj[1] pcr[106] option 0 option 1 option 2 option 3 gpio[106] viu1_pdi_hsync emios1[9] emios0[8] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 44 u4 pj[2] pcr[107] option 0 option 1 option 2 option 3 gpio[107] viu0_pdi_vsync emios1[14] emios0[9] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 55 u3 pj[3] pcr[108] option 0 option 1 option 2 option 3 gpio[108] viu_pclk emios0[22] pdi_de ?siul viu2 pwm/timer pdi i/o s none, none 60 72 ad15 pj[4] pcr[109] option 0 option 1 option 2 option 3 gpio[109] viu2_pdi0 emios0[21] emios0[23] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 56 68 ad14 pj[5] pcr[110] option 0 option 1 option 2 option 3 gpio[110] viu3_pdi1 emios0[20] emios0[16] ?siul viu2/pdi pwm/timer pwm/timer i/o m none, none 57 69 ae14 pj[6] pcr[111] option 0 option 1 option 2 option 3 gpio[111] viu4_pdi2 emios0[19] emios0[15] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 58 70 af14 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 50 pj[7] pcr[112] option 0 option 1 option 2 option 3 gpio[112] viu5_pdi3 emios0[18] emios0[14] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 59 71 ac15 pj[8] pcr[113] option 0 option 1 option 2 option 3 gpio[113] viu6_pdi4 emios0[17] emios0[13] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 88 u2 pj[9] pcr[114] option 0 option 1 option 2 option 3 gpio[114] viu7_pdi5 emios1[22] emios0[12] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 99 u1 pj[10] pcr[115] option 0 option 1 option 2 option 3 gpio[115] viu8_pdi6 emios1[17] emios0[11] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 10 10 v4 pj[11] pcr[116] option 0 option 1 option 2 option 3 gpio[116] viu9_pdi7 emios1[15] emios0[10] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 11 11 v3 pj[12] pcr[117] option 0 option 1 option 2 option 3 gpio[117] dcu_tag ? dculite_g6 ?siul dcu3 ? dculite i/o m none, none 148 178 a23 pj[13] pcr[118] option 0 option 1 option 2 option 3 gpio[118] quadspi_pcs_b emios1[8] viu5_pdi13 ?siul quadspi pwm/timer viu2/pdi i/o m none, none 149 179 d22 pj[14] pcr[119] option 0 option 1 option 2 option 3 gpio[119] quadspi_clk_b emios1[17] pdi_pclk ?siul quadspi pwm/timer pdi i/o f none, none 150 180 c22 pj[15] pcr[120] option 0 option 1 option 2 option 3 gpio[120] quadspi_io3_b emios1[9] viu6_pdi14 ?siul quadspi pwm/timer viu2/pdi i/o m none, none 151 181 b22 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 51 port k pk[0] pcr[121] option 0 option 1 option 2 option 3 gpio[121] emios1[18]] ? ? ?siul pwm/timer ? ? i/o m none, none 155 187 a21 pk[1] pcr[122] option 0 option 1 option 2 option 3 gpio[122] quadspi_io2_b emios1[14] viu7_pdi15 ?siul quadspi pwm/timer viu2/pdi i/o m none, none 156 188 d20 pk[2] pcr[123] option 0 option 1 option 2 option 3 gpio[123] viu0_pdi8 emios1[10] dculite_tag ?siul viu2/pdi pwm/timer dculite i/o m none, none 31 39 ae3 pk[3] pcr[124] option 0 option 1 option 2 option 3 gpio[124] viu1_pdi9 emios1[11] dculite_de ?siul viu2/pdi pwm/timer dculite i/o m none, none 32 40 af3 pk[4] pcr[125] option 0 option 1 option 2 option 3 gpio[125] viu2_pdi10 emios1[12] dculite_hsync ?siul viu2/pdi pwm/timer dculite i/o m none, none 33 41 ac4 pk[5] pcr[126] option 0 option 1 option 2 option 3 gpio[126] viu3_pdi11 emios1[13] dculite_vsync ?siul viu2/pdi pwm/timer dculite i/o m none, none 34 42 af4 pk[6] pcr[127] option 0 option 1 option 2 option 3 gpio[127] viu4_pdi12 emios1[9] dculite_pclk ?siul viu2/pdi pwm/timer dculite i/o f none, none 35 43 ac5 pk[7] pcr[128] option 0 option 1 option 2 option 3 gpio[128] rxd_2 dculite_r2 tcon[8] ?siul linflex_2 dculite tcon i/o m none, none ?44 ad5 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 52 pk[8] pcr[129] option 0 option 1 option 2 option 3 gpio[129] txd_2 dculite_r3 tcon[9] ?siul linflex_2 dculite tcon i/o m none, none ? 45 ae5 pk[9] pcr[130] option 0 option 1 option 2 option 3 gpio[130] i2s_do / pwmo dculite_r4 tcon[10] ?siul sgm dculite tcon i/o m none, none ?46 af5 pk[10] pcr[131] option 0 option 1 option 2 option 3 gpio[131] sda_1 emios1[12] dculite_tag ?siul i 2 c_1 pwm/timer dculite i/o s none, none 51 59 af8 pk[11] pcr[132] option 0 option 1 option 2 option 3 gpio[132] scl_1 emios1[13] dcu_tag / tcon[3] ?siul i 2 c_1 pwm/timer dcu3 / tcon i/o s none, none 52 60 ac9 pk[12] ? ? reserved ? ? ? ? ? ? ? ? pk[13] ? ? reserved ? ? ? ? ? ? ? ? pk[14] ? ? reserved ? ? ? ? ? ? ? ? pk[15] ? ? reserved ? ? ? ? ? ? ? ? port l pl[0] pcr[133] option 0 option 1 option 2 option 3 gpio[133] ? canrx_1 ? ans[19] siul ? flexcan_1 ? i/o m / analo g none, none ? 81 ae22 pl[1] pcr[134] option 0 option 1 option 2 option 3 gpio[134] ? cantx_1 ? ans[18] siul ? flexcan_1 ? i/o m / analo g none, none ? 82 ae21 pl[2] pcr[135] option 0 option 1 option 2 option 3 gpio[135] ? canrx_0 emios1[22] ans[17] siul ? flexcan_0 pwm/timer i/o s / analo g none, none ?83 af22 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 53 pl[3] pcr[136] option 0 option 1 option 2 option 3 gpio[136] ? cantx_0 emios1[23] ans[16] siul ? flexcan_0 pwm/timer i/o s / analo g none, none ?84 af21 pl[4] pcr[137] option 0 option 1 option 2 option 3 gpio[137] cs2_2 viu5_pdi13 tcon[6] ?siul dspi_2 viu2/pdi tcon i/o m none, none ? 31 ab2 pl[5] pcr[138] option 0 option 1 option 2 option 3 gpio[138] cs1_2 viu6_pdi14 tcon[7] ?siul dspi_2 viu2/pdi tcon i/o m none, none ?32 ac2 pl[6] pcr[139] option 0 option 1 option 2 option 3 gpio[139] cs0_2 viu7_pdi15 emios1[18] ?siul dspi_2 viu2/pdi pwm/timer i/o s none, none ?33 ad1 pl[7] pcr[140] option 0 option 1 option 2 option 3 gpio[140] sin_2 viu8_pdi16 emios1[19] ?siul dspi_2 viu2/pdi pwm/timer i/o s none, none ? 34 ae1 pl[8] pcr[141] option 0 option 1 option 2 option 3 gpio[141] sout_2 viu9_pdi17 emios1[20] ?siul dspi_2 viu2/pdi pwm/timer i/o s none, none ?35 af1 pl[9] pcr[142] option 0 option 1 option 2 option 3 gpio[142] sck_2 pdi_pclk emios1[21] ?siul dspi_2 pdi pwm/timer i/o s none, none ?36 af2 pl[10] pcr[143] option 0 option 1 option 2 option 3 gpio[143] emios1[10] dculite_g2 ? ?siul pwm/timer dculite ? i/o m none, none ? 174 c24 pl[11] pcr[144] option 0 option 1 option 2 option 3 gpio[144] emios1[11] dculite_g3 ? ?siul pwm/timer dculite ? i/o m none, none ? 175 a24 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 54 pl[12] pcr[145] option 0 option 1 option 2 option 3 gpio[145] emios1[12] dculite_g4 ? ?siul pwm/timer dculite ? i/o m none, none ? 176 c23 pl[13] pcr[146] option 0 option 1 option 2 option 3 gpio[146] emios1[13] dculite_g5 ? ?siul pwm/timer dculite ? i/o m none, none ? 177 b23 pl[14] ? ? reserved ? ? ? ? ? ? ? ? pl[15] ? ? reserved ? ? ? ? ? ? ? ? port m pm[0] pcr[147] option 0 option 1 option 2 option 3 gpio[147] i2s_sck / pwmoa dculite_r5 tcon[11] ?siul sgm dculite tcon i/o m none, none ? 61 ae9 pm[1] pcr[148] option 0 option 1 option 2 option 3 gpio[148] i2s_fs dculite_r6 ? ?siul sgm dculite ? i/o m none, none ?62 af9 pm[2] pcr[149] option 0 option 1 option 2 option 3 gpio[149] emios1[17] dculite_r7 dculite_de rsdsclkm siul pwm/timer dculite dculite i/o m none, none ? 173 d23 pm[3] pcr[150] option 0 option 1 option 2 option 3 gpio[150] canrx_2 rxd_3 tcon[4] ?siul flexcan_2 linflex_3 tcon i/o m none, none ?16 y3 pm[4] pcr[151] option 0 option 1 option 2 option 3 gpio[151] cantx_2 txd_3 tcon[5] ?siul flexcan_2 linflex_3 tcon i/o m none, none ?17 y2 pm[5] pcr[152] option 0 option 1 option 2 option 3 gpio[152] viu5_pdi13 emios1[22] dcu_tag ?siul viu2/pdi pwm/timer dcu3 i/o m none, none 16 ? ? table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 55 pm[6] pcr[153] option 0 option 1 option 2 option 3 gpio[153] viu6_pdi14 emios1[23] dculite_tag ?siul viu2/pdi pwm/timer dculite i/o m none, none 17 ? ? pm[7] pcr[154] option 0 option 1 option 2 option 3 gpio[154] viu8_pdi16 i2s_do / pwmo emios1[16] ?siul viu2/pdi sgm pwm/timer i/o s none, none 39 ? ? pm[8] pcr[155] option 0 option 1 option 2 option 3 gpio[155] viu9_pdi17 i2s_sck / pwmoa emios1[23] ?siul viu2/pdi sgm pwm/timer i/o s none, none 40 ? ? pm[9] pcr[156] option 0 option 1 option 2 option 3 gpio[156] pdi_pclk sgm_mclk emios0[8] ?siul pdi sgm pwm/timer i/o m none, none 113 ? ? pm[10] pcr[157] option 0 option 1 option 2 option 3 gpio[157] rxd_2 canrx_2 emios0[16] ?siul linflex_2 flexcan_2 pwm/timer i/o s none, none 114 ? ? pm[11] pcr[158] option 0 option 1 option 2 option 3 gpio[158] txd_2 cantx_2 emios0[23] ?siul linflex_2 flexcan_2 pwm/timer i/o s none, none 115 ? ? pm[12] pcr[159] option 0 option 1 option 2 option 3 gpio[159] dculite_b7 ? i2s_sck / pwmoa ?siul dculite ? sgm i/o m none, none ? ? l24 pm[13] pcr[160] option 0 option 1 option 2 option 3 gpio[160] dculite_pclk ? sgm_mclk ?siul dculite ? sgm i/o f none, none ? ? l23 pm[14] ? ? reserved ? ? ? ? ? ? ? ? pm[15] ? ? reserved ? ? ? ? ? ? ? ? table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 56 port n pn[0] pcr[161] option 0 option 1 option 2 option 3 gpio[161] dculite_hsync ? tcon[4] ?siul dculite ? tcon i/o m none, none ?? ac3 pn[1] pcr[162] option 0 option 1 option 2 option 3 gpio[162] dculite_vsync ? tcon[5] ?siul dculite ? tcon i/o m none, none ?? ad3 pn[2] pcr[163] option 0 option 1 option 2 option 3 gpio[163] dculite_r0 rxd_2 viu0_pdi8 ?siul dculite linflex_2 viu2/pdi i/o m none, none ?? ac10 pn[3] pcr[164] option 0 option 1 option 2 option 3 gpio[164] dculite_r1 txd_2 viu1_pdi9 ?siul dculite linflex_2 viu2/pdi i/o m none, none ?? af10 pn[4] pcr[165] option 0 option 1 option 2 option 3 gpio[165] dculite_r2 ? tcon[6] ?siul dculite ? tcon i/o m none, none ?? ac11 pn[5] pcr[166] option 0 option 1 option 2 option 3 gpio[166] dculite_r3 ? tcon[7] ?siul dculite ? tcon i/o m none, none ?? ad11 pn[6] pcr[167] option 0 option 1 option 2 option 3 gpio[167] dculite_r4 ? tcon[8] ?siul dculite ? tcon i/o m none, none ? ? ae11 pn[7] pcr[168] option 0 option 1 option 2 option 3 gpio[168] dcu_lite_r5 ? tcon[9] ?siul dculite ? tcon i/o m none, none ?? af11 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 57 pn[8] pcr[169] option 0 option 1 option 2 option 3 gpio[169] dculite_r6 ? tcon[10] ?siul dculite ? tcon i/o m none, none ?? ac12 pn[9] pcr[170] option 0 option 1 option 2 option 3 gpio[170] dculite_r7 ? tcon[11] ?siul dculite ? tcon i/o m none, none ?? ad12 pn[10] pcr[171] option 0 option 1 option 2 option 3 gpio[171] dculite_g0 rxd_3 viu2_pdi10 ?siul dculite linflex_3 viu2/pdi i/o m none, none ? ? ae12 pn[11] pcr[172] option 0 option 1 option 2 option 3 gpio[172] dculite_g1 txd_3 viu3_pdi11 ?siul dculite linflex_3 viu2/pdi i/o m none, none ?? af12 pn[12] pcr[173] option 0 option 1 option 2 option 3 gpio[173] dculite_g2 ? emios0[17] ?siul dculite ? pwm/timer i/o m none, none ?? r26 pn[13] pcr[174] option 0 option 1 option 2 option 3 gpio[174] dculite_g3 ? emios0[18] ?siul dculite ? pwm/timer i/o m none, none ?? r25 pn[14] pcr[175] option 0 option 1 option 2 option 3 gpio[175] dculite_g4 ? emios0[19] ?siul dculite ? pwm/timer i/o m none, none ?? p26 pn[15] pcr[176] option 0 option 1 option 2 option 3 gpio[176] dculite_g5 ? emios0[20] ?siul dculite ? pwm/timer i/o m none, none ?? p24 port p pp[0] pcr[177] option 0 option 1 option 2 option 3 gpio[177] dculite_g6 ? emios0[21] ?siul dculite ? pwm/timer i/o m none, none ?? p23 table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 58 pp[1] pcr[178] option 0 option 1 option 2 option 3 gpio[178] dculite_g7 ? emios0[22] ?siul dculite ? pwm/timer i/o m none, none ?? n26 pp[2] pcr[179] option 0 option 1 option 2 option 3 gpio[179] dculite_b0 canrx_2 viu4_pdi12 ?siul dculite flexcan_2 viu2/pdi i/o m none, none ?? n25 pp[3] pcr[180] option 0 option 1 option 2 option 3 gpio[180] dculite_b1 cantx_2 pdi_de ?siul dculite flexcan_2 pdi i/o m none, none ?? n23 pp[4] pcr[181] option 0 option 1 option 2 option 3 gpio[181] dculite_b2 ? emios0[11] ?siul dculite ? pwm/timer i/o m none, none ?? m26 pp[5] pcr[182] option 0 option 1 option 2 option 3 gpio[182] dculite_b3 ? emios0[13] ?siul dculite ? pwm/timer i/o m none, none ?? m25 pp[6] pcr[183] option 0 option 1 option 2 option 3 gpio[183] dculite_b4 ? emios0[15] ?siul dculite ? pwm/timer i/o m none, none ?? m24 pp[7] pcr[184] option 0 option 1 option 2 option 3 gpio[184] dculite_b5 ? i2s_fs ?siul dculite ? sgm i/o m none, none ?? m23 pp[8] ? ? reserved ? ? ? ? ? ? ? ? pp[9] ? ? reserved ? ? ? ? ? ? ? ? pp[10] ? ? reserved ? ? ? ? ? ? ? ? pp[11] ? ? reserved ? ? ? ? ? ? ? ? table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pinout and signal descriptions PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 59 pp[12] ? ? reserved ? ? ? ? ? ? ? ? pp[13] ? ? reserved ? ? ? ? ? ? ? ? pp[14] ? ? reserved ? ? ? ? ? ? ? ? pp[15] ? ? reserved ? ? ? ? ? ? ? ? 1 alternate functions are chosen by setting the values of the pcr[pa] bitfields inside the siul module. pcr[pa] = 00 selects option 0 pcr[pa] = 01 selects option 1 pcr[pa] = 10 selects option 2 pcr[pa] = 11 selects option 3 this is intended to select the output functions. to use one of the input functions, the pcr[ibe] bit must be written to ?1?, re gardless of the values selected in the pcr[pa] bitfields. for this reason, the value corresponding to an input only function is reported as ???. 2 special functions are enabled independently from the standard di gital pin functions. enabling standard i/o functions in the pcr registers may interfere with their functionality. adc functions are enabled using the pcr[apc] bit; other functions are enabled by enabling the respective m odule. 3 using the psmi registers in the system integr ation unit lite (siul), different pads can be multiplexed to the same peripheral i nput. please see the siul chapter of the PXD20 microcontroller reference manual for details. 4 see the ?pad types? section for an explanation of the letters in this column. 5 reset configuration is given as i/o direction and pull, e.g., ?input, pullup?. 6 out of reset pins ph[0:3] are available as jtag pins (tck, tdi, td o and tms respectively). it is up to the user to configure pi ns ph[0:3] when needed. table 7. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
system design information PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 60 3 system design information 3.1 power-up sequencing the preferred power-up sequence for PXD20 is as follows: 1. generic io supplies or noise-free supplies, consisting of: ? vdda ? vdde_a ? vdde_b ? vddm ? vdd_dr ? vdd33_dr ? vddpll figure 6. power-up sequencing
system design information PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 61 figure 7. power-down sequencing 2. all 3.3v supplies (vdde_b and vdd33_dr) should be ramped up first, and then the rest of the i/o supplies should be ramped up (vdda, vdde_a, vddm, and vdd_dr). 3. vddr, the regulator input supply, should be the last supply to ramp up; all supplies can be ramped up together as long as vddr is included. so all 5v supplies should be ramped up after the 3.3 v supplies, and if all the supplies are of the same level, they can be ramped up together as well. 4. lv supply (vdd12). if vreg is in bypass mode and the core supply (1.2 v) is supplied externally, then this should be the last supply given. note for ddr, the 3.3 v supply (vdd33_dr) should come before vdd_dr. this sequence ensures that when vreg releases its lvds, th e io and other hv segments are powered properly. this is important becau se PXD20 doesn't moni tor lvds on io hv supplies.
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 62 4 electrical characteristics 4.1 introduction this section contains electrical char acteristics of the device as well as temperature and power considerations. this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to tak e precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be driven to an appropriate logic voltage level (v dd or v ss ). this could be done by internal pull up and pull down, which is provided by the product for most general purpose pins. the parameters listed in the following tables represent th e characteristics of the device and its demands on the system. in the tables where the device lo gic provides signals with their respective timing characteristics, the symbol ?cc? for control ler characteristics is included in the symbol column. in the tables where the external system mu st provide signals with their respective timing characteristics to the device, the sy mbol ?sr? for system requirement is included in the symbol column. 4.2 parameter classification the electrical parameters shown in this supplem ent are guaranteed by various methods. to give the customer a bette r understanding, the classi fications listed in table 8 are used and the parameters are tagged accordingly in the tabl es where appropriate. note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. table 8. paramete r classifications classification ta g tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations.
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 63 4.3 absolute maximum ratings table 9. absolute maximum ratings symbol c parameter conditions value unit specid min max v dda sr d voltage on vdda pin (adc reference) with respect to ground (v ssa ) ?0.3 +5.5 v d1.1 relative to v dd v dd ?0.3 v dd +0.3 v ssa sr d voltage on vssa (adc reference) pin with respect v ss v ss ?0.1 v ss +0.1 v d1.2 v ddpll cc d voltage on vddpll (1.2 v pll supply) pin with respect to ground (v sspll ) 1.08 1.32 v d1.3 relative to v dd v dd ?0.3 v dd +0.3 v ddr sr d voltage on vddr pin (regulator supply) with respect to ground (v ssr ) ?0.3 +5.5 v d1.4 relative to v dd v dd ?0.3 v dd +0.3 v ssr sr d voltage on vssr (regulator ground) pin with respect to v ss v ss ?0.1 v ss +0.1 v d1.5 v dd12 cc d voltage on vdd12 pin with respect to ground (v ss12 ) 1.08 1.4 v d1.6 v ss12 cc d voltage on vss12 pin with respect to v ss v ss ?0.1 v ss +0.1 v d1.7 v dde_a 1 1 throughout the remainder of this document v dd refers collectively to i/o voltage supplies, i.e., v dde_a , v dde_b , and v ddm , unless otherwise noted. sr d voltage on vdde_a (i/o supply) pin with respect to ground (v sse_a ) ?0.3 +5.5 v d1.8 v dde_b 1 sr d voltage on vdde_b (i/o supply) pin with respect to ground (v ss ) ?0.3 +3.6 v d1.9 v ddm 1 sr d voltage on vddm (stepper motor supply) pin with respect to ground (v ssm ) ?0.3 +5.5 v d1.10 v ss 2 2 throughout the remainder of this document v ss refers collectively to i/o voltage supply grounds, i.e., v sse_a , v sspll , and v ssm , unless otherwise noted. sr d i/o supply ground 0 0 v d1.11 v dd_dr d voltage on v ddddr with respect to v ss ?0.3 3.6 v d1.12 v rsds d voltage on v ddrsds with respect to v ss ?0.3 3.6 v d1.13 v in sr d voltage on any gpio pin with respect to ground (v ss ) ?0.3 v ddmax (v dde max of that segment) v i injpad sr d injected input current on any pin during overload condition ?10 10 ma d1.15 i injsum sr d absolute sum of all injected input currents during overload condition ?50 50 d1.16 t storage sr t storage temperature ?55 150 c d1.17 esd hbm sr t esd susceptibility (human body model) 2000 v d1.18
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 64 note stresses exceeding the recommended absolute maximum ratings ma y cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi cated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v dd or v in electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 65 1 100 nf capacitance needs to be provided between v dda /v ssa pair. 2 10 ? f capacitance must be connected between v ddr and v ss12 because of a sharp surge due to external ballast. 3 v dd12 cannot be used to drive any external component. 4 each v dd12 /v ss12 supply pair should have a 10 ? f capacitor. absolute combined maximum capacitance is 40 ? f. preferably, all the vdd12 supply pads should be shorted and then connected to a 4 ? 10 ? f capacitance. this is to ensure the esr of external capacitance does not exceed 0.2 ? . a 100 nf capacitor must be placed close to the pin. 5 v dd refers collectively to i/o voltage supplies, i.e., v dde_a , v dde_b , v dd_dr , and v ddm . 6 100 nf capacitance needs to be provided between each v dd /v ss pair. vddmin value for is 3 v for vdde_a & vddm as well as for vdde_b, while it is 1.62 v for vdd_dr. vdd max va lue is 3.6 v for vdde_a & vddm as well as for vdde_b & vdd_dr. 7 full electrical specification cannot be guaranteed when voltage dr ops below 3.0v. in particular, adc electrical characteristics and i/o?s dc electrical specification may not be guaranteed. when voltage drops below v lv d h vl device is reset. 8 v ss refers collectively to i/o voltage supply grounds, i.e., v sse_a , v ss , and v ssm unless otherwise noted. 9 v dde_a should not be less than v dda . 10 guaranteed by device validation. table 11. recommended operating conditions (5.0 v) symbol c parameter conditions value unit specid min max v dda 1 sr p voltage on vdda pin (adc reference) with re- spect to ground (v ss ) +4.5 +5.5 v d2.19 d voltage drop 2 +3.0 +5.5 d relative to v dd v dd ?0.1 v dd +0.1 v ssa sr d voltage on vssa (adc reference) pin with respect v ss v ss ?0.1 v ss +0.1 v d2.20 v ddpll cc p voltage on vddpll (1.2 v pll supply) pin with respect to ground (v sspll ) 1.08 1.32 v d2.21 v ddr 3 sr p voltage on vddr pin (regulator supply) with respect to ground (v ssr ) +3.0 +3.6 v d2.22 d voltage drop 2 +3.0 +3.6 d relative to v dd v dd ?0.1 v dd +0.1 v ssr sr d voltage on vssr (regulator ground) pin with respect to v ss v ss ?0.1 v ss +0.1 v d2.23 v dd12 4,5 cc p voltage on vdd12 pin with respect to ground (v ss12 ) 1.08 1.4 v d2.24 v ss12 cc d voltage on vss12 pi n with respect to v ss v ss ?0.1 v ss +0.1 v d2.25 v dd 6,7 sr p voltage on vdd pins (vdde_a, vdde_b, vdd_dr, vddma, vddmb, vddmc) with respect to ground (v ss ) voltage drop 2 v ddmin 6 v ddmax 6 vd2.26 v ss 8 sr d i/o supply ground 0 0 v d2.27 v dde_a 9 sr p voltage on vdde_a (i/o supply) pin with respect to ground (v sse_a ) +4.5 +5.5 v d2.28 v dde_b 10 sr p voltage on vdde_b (i/o supply) pin with respect to ground (v sse_b +3.0 +3.6 v d2.29
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 66 4.5 thermal characteristics v ddm sr p voltage on vddma (stepper motor supply) pin with respect to ground (v ssma ) +4.5 +5.5 v d2.30 v dd_dr 11 p voltage on v dd_dr with respect to v ss +1.62 +3.6 v d2.31 v ss_dr d voltage on v ssrsds with respect to v ss +1.62 +3.6 v d2.32 v rsds p voltage on v dd_dr with respect to v ss +3.0 +3.6 v d2.33 tv dd sr d v dd slope to ensure correct power up 12 12 v/ms d2.34 t a sr p ambient temperature under bias ?40 105 c d2.35 ?40 105 t j sr d junction temperature under bias ?40 140 d2.36 1 100 nf capacitance needs to be provided between v dda /v ssa pair. 2 full functionality cannot be guaranteed when voltage drops below 4. 5 v. in particular, i/o dc and adc electrical characteristics may not be guaranteed below 4.5 v during the voltage drop sequence. 3 10 ? f capacitance must be connected between v ddr and v ss12 . it is recommended that this cap should be placed, as close as possible to the dut pin on board. 4 v dd12 cannot be used to drive any external component. 5 each v dd12 /v ss12 supply pair should have a 10 ? f capacitor. absolute combin ed maximum capacitance is 40 ? f. preferably, all the vdd12 supply pads should be shorted and then connected to a 4 ? 10 ? f capacitance. this is to ensure the esr of external capacitance does not exceed 0.2 ? . a 100 nf capacitor must be placed close to the pin. 6 v dd refers collectively to i/o voltage supplies, i.e., v dde_a , v dde_b , v dde_dr , v ddma , v ddmb and v ddmc . vddmin value for is 4.5 v for vdde_a & vddm, 3 v vdde_b, while it is 1.62 v for vdd_dr. vdd max value is 5.5 v for vdde_a & vddm and 3.6 v for vdde_b & vdd_dr. 7 100 nf capacitance needs to be provided between each v dd /v ss pair. 8 v ss refers collectively to i/o voltage supply grounds, i.e., v sse_a , v sse_b , v sse_a , v sse_e , v ssma , v ssmb and v ssmc ) unless otherwise noted. 9 v dde_a should not be less than v dda . 10 vdde_b cannot go beyond 3.6v under any operating condition. 11 vdd_dr can be 1.8, 2.5 and 3.3v (typic al) based on type of sdr memory. 12 guaranteed by device validation table 12. thermal characteristics for 176-pin lqfp 1 symbol c parameter conditions value unit specid r ? ja cc d junction to ambient natural convection 2 single layer board ?1s 36 c/w d3.1 r ? ja cc d junction to ambient natural convection 2 four layer board ?2s2p 29 c/w d3.2 r ? jma cc d junction to ambient 2 @200 ft./min., single layer board ?1s 28 c/w d3.3 r ? jma cc d junction to ambient 2 @200 ft./min., four layer board ?2s2p 23 c/w d3.4 r ? jb cc d junction to board 3 18 c/w d3.5 r ? jctop cc d junction to case (top) 4 5c/wd3.6 table 11. recommended operating conditions (5.0 v) (continued) symbol c parameter conditions value unit specid min max
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 67 ? jt cc d junction to package top natural convec- tion 5 2c/wd3.7 1 thermal characteristics are targets based on simulation t hat are subject to change per device characterization. 2 junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 3 junction-to-board thermal resistance determined per jedec j esd51-8. thermal test board me ets jedec specification for the specified package. 4 junction-to-case at the top of the package determined using mil-std 883 method 1012. 1. the cold plate temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer. 5 thermal characterization parameter indicating the temper ature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not ava ilable, the thermal characterization parameter is written as psi-jt. table 13. thermal characteristics for 208-pin lqfp 1 1 thermal characteristics are targets based on simulation th at are subject to change per device characterization. symbol c parameter conditions value unit specid r ? ja cc d junction to ambient natural convection 2 2 junction-to-ambient thermal resistance determined per jede c jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. single layer board ?1s 34 c/w d3.8 r ? ja cc d junction to ambient natural convection 2 four layer board ?2s2p 27 c/w d3.9 r ? jma cc d junction to ambient 2 @200 ft./min., single layer board ?1s 27 c/w d3.10 r ? jma cc d junction to ambient 2 @200 ft./min., four layer board ?2s2p 22 c/w d3.11 r ? jb cc d junction to board 3 3 junction-to-board thermal resistance dete rmined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. ? 18 c/w d3.12 r ? jctop cc d junction to case (top) 4 4 junction-to-case at the top of the packa ge determined using mil-std 883 method 1012. 1. the cold plate temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer. ? 5 c/w d3.13 ? jt cc d junction to package top natural convec- tion 5 5 thermal characterization parameter indicating the temperat ure difference between the package top and the junction temperature per jedec jesd51-2. when gree k letters are not available, the thermal characterization parameter is written as psi-jt. ? 2 c/w d3.14 table 14. thermal characteristics for 416-pin tepbga 1 symbol c parameter conditions value unit specid r ? ja cc d junction to ambient natural convection 2 single layer board ?1s 26 c/w d3.15 r ? ja cc d junction to ambient natural convection 2 four layer board ?2s2p 18 c/w d3.16 r ? jma cc d junction to ambient 2 @200 ft./min., single layer board ?1s 20 c/w d3.17 r ? jma cc d junction to ambient 2 @200 ft./min., four layer board ?2s2p 15 c/w d3.18 r ? jb cc d junction to board 3 ? 10 c/w d3.19 r ? jctop cc d junction to case (top) 4 ? 6 c/w d3.20 table 12. thermal characteristics for 176-pin lqfp 1 (continued) symbol c parameter conditions value unit specid
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 68 4.5.1 general notes for specification s at maximum junction temperature an estimate of the chip junction temperature, t j , can be obtained from the equation: t j = t a + (r ? ja * p d ) eqn. 1 where: t a = ambient temperature for the package ( o c) r ? ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the thermal resistance values used are based on the jedec jesd 51 series of standards to provide consistent values for estimations and comparisons. th e difference between the values determined fo r the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a grou nd plane (2s2p), demonstrate that the effective thermal resistan ce is not a constant. the therma l resistance depends on the: ? construction of the application board (number of planes) ? effective size of the boar d which cools the component ? quality of the thermal and elect rical connections to the planes ? power dissipated by adjacent components connect all the ground and power balls to the respective planes with one via per ball. using fewer vias to connect the package to the planes reduces the thermal perfor mance. thinner planes also reduce the thermal performance. when the clearance between the vias leave the planes virtually disconnected, the thermal pe rformance is also greatly reduced. as a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. the value obtained on a board with the internal planes is usually within the normal range if the application board has: ? one oz. (35 micron nominal thickness) internal planes ? components are well separated ? overall power dissipation on the board is less than 0.02 w/cm2 the thermal performance of any component depends on the power dissipation of the surrounding components. in addition, the ambient temperature varies widely within the application. for many natural conv ection and especially cl osed box applications, the board temperature at the perimeter (edge ) of the package is approxim ately the same as the loca l air temperature near the device. specifying the local ambi ent conditions explicitly as th e board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. ? jt cc d junction to package top natural convec- tion 5 ? 2 c/w d3.21 1 thermal characteristics are targets based on simulation t hat are subject to change per device characterization. 2 junction-to-ambient thermal resistan ce determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 3 junction-to-board thermal resistance determined per jedec j esd51-8. thermal test board me ets jedec specification for the specified package. 4 junction-to-case at the top of the package determined using mi l-std 883 method 1012.1. the co ld plate temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer. 5 thermal characterization parameter indicating the temper ature difference between t he package top and the junction temperature per jedec jesd51-2. when greek letters are not ava ilable, the thermal characterization parameter is written as psi-jt. table 14. thermal characteristics for 416-pin tepbga 1 (continued) symbol c parameter conditions value unit specid
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 69 at a known board temperature, the junction temperature is estimated using the following equation: t j = t b + (r ? jb * p d ) eqn. 2 where: t b = board temperature for the package perimeter ( o c) r ? jb = junction-to-board thermal resistance ( o c/w) per jesd51-8s p d = power dissipation in the package (w) when the heat loss from the package case to the air does not factor in to the calculation, an accep table value for the junction temperature is predictable. ensure the appl ication board is similar to the thermal te st condition, with the component soldered to a board with internal planes. the thermal resistance is expressed as the sum of a junctio n-to-case thermal resistance pl us a case-to-ambient thermal resistance: r ? ja = r ? jc + r ? ca eqn. 3 where: r ? ja = junction to ambient thermal resistance ( o c/w) r ? jc = junction to case thermal resistance ( o c/w) r ? ca = case to ambient thermal resistance ( o c/w) r ? jc s device related and is not affected by other factors. the thermal environment can be controlled to change the case-to-ambient thermal resistance, r ? ca . for example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. this description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. for most pack ages, a better model is required. a more accurate two-resistor thermal model can be construc ted from the junction-to-board thermal resistance and the junction-to-case thermal resistance. the junction-to-case thermal resistance descri bes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. the junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the pr inted circuit board. this model can be used to generate simple estimations and for computational fluid dynamics (cfd) thermal models. to determine the junction temperature of th e device in the application on a prototyp e board, use the thermal characterization parameter ( ? jt ) to determine the junction temperature by measuring the temperature at the top cente r of the package case using the following equation: t j = t t + ( ? jt x p d ) eqn. 4 where: t t = thermocouple temperature on top of the package ( o c) ? jt = thermal characterization parameter ( o c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured in compli ance with the jesd51-2 specificat ion using a 40-gauge type t thermocouple epoxied to the top center of the package case. positio n the thermocouple so that the thermocouple junction rests on the package. place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. place the thermocoup le wire flat against the package case to avoi d measurement errors caused by the cooling effects of the thermocouple wire. references:
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 70 semiconductor equipment and materials international 805 east middlefield rd. mountain view, ca 94043 (415) 964-5111 mil-spec and eia/jesd (jedec) specifi cations are available from global engi neering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org . 4.6 emi (electromagnetic interference) characteristics 4.7 power management 4.7.1 voltage regulator electrical characteristics the internal voltage regulator requires an external np n (bcp68 or njd2873) ballast to be connected as shown in figure 8 s well as an external capacitance (c reg ) to be connected to the device in order to provide a stable low voltage digital supply to the device. capacitances should be placed on the board as near as possible to the associ ated pins. care should also be taken to limit the serial inductance of the board to less than 15 nh. table 15. emi testing specifications 12 1 the reported emission level is the value of the ma ximum emission, rounded up to the next whole number. 2 iec level maximum:, l is less than or equal to 24 dbv, k is less than or equal to 30 dbv. symbol parameter conditions clocks frequency range level (typ) unit radiated emissions v eme device configuration, test conditions and em testing per standard iec61967-2 fosc ? 8 mhz, external crystal fcpu ?124 mhz fbus ?124 mhz no pll frequency modulation 150 khz ? 50 mhz 19 dbv 50 mhz ? 150 mhz 30 150 mhz ? 500 mhz 25 500 mhz ? 1000 mhz 19 iec level k fosc ? 8 mhz, external crystal fcpu ?124 mhz fbus ?124 mhz 2% pll frequency modulation 150 khz ? 50 mhz 15 dbv 50 mhz ? 150 mhz 24 150 mhz ? 500 mhz 17 500 mhz ? 1000 mhz 14 iec level l
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 71 for the PXD20 microcontroller, 10 0 nf should be placed between each v dd12 /v ss12 supply pair and also between the v ddpll /v sspll pair. additionally, 10 ? f should be placed between the v ddr pin and the adjacent v ss pin. v ddr = 3.0 v to 3.6 v / 4.5 v to 5.5 v, t a = ?40 to 105 c, unless otherwise specified. figure 8. external npn ballast connections table 16. voltage regulator electrical characteristics symbol c parameter conditions min max unit specid v ddr sr p power supply ? 3.0 5.5 v d5.1 t j sr d junction temperature ? ?40 140 c d5.2 i reg cc t current consumption reference included, @ 55 c no load @ full load ? 2 11 ma d5.3 i l cc t output current capacity dc load current ? 450 ma d5.4 v dd12 cc d output voltage (value @ i l = 0 @ 27c) pre-trimming sigma < 7 mv ? 1.330 v d5.5 p post-trimming 1.26 1.29 t output voltage (value @ i l = imax) post-trimming 1.145 ? sr d external decoupling/stability capacitor 4 capacitances of 10 f each 10 4 ? f d5.6 d esr of external cap 0.05 0.2 ohm d 1 bond wire r + 1 pad r 0.2 1 ohm l bond cc d bonding inductance for bipolar base control pad 0 15 nh d5.7 cc d power supply rejection @ dc @ no load cload = 10 f 4 ? ?30 db d5.8 d @ 200 khz @ no load ?100 d@ dc @ 400ma ?30 d @ 200 khz @ 400 ma ?30 cc d load current transient cload = 10 f 4 ? 10% to 90% of i l (max) in 100 ns d5.9 t su cc t start-up time after input supply stabilizes 1 cload = 10 f 4 ? 500 s d5.10 vrc_ctrl v ddr v dd12
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 72 4.7.2 voltage monitor electrical characteristics the device implements a power on reset module to ensure correct power-up initialization, as well as four low voltage detectors to monitor the v dd and the v dd12 voltage while device is supplied: ? por monitors v dd during the power-up phase to ensure devi ce is maintained in a safe reset state ? lvdhv3 monitors v dd to ensure device reset below minimum functional supply ? lvdhv5 monitors v dd when application uses devi ce in the 5.0v 10% range ? lvdlvcor monitors power domain no. 1 ? lvdlvbkp monitors power domain no. 0 1 time after the input supply to the voltage regulator has ramped up (vddr) and the voltage regulator has asserted the power ok signal. table 17. low-power voltage regulator electrical characteristics symbol c parameter conditions min max unit specid t j sr d junction temperature ? ?40 140 c d5.2 i reg cc t current consumption reference included, @ 55 c no load @ full load ? 5 600 a d5.3 i l cc t output current capacity dc load current ? 15 ma d5.4 v dd12 cc d output voltage pre-trimming sigma < 7 mv ? 1.33 v d5.5 p post-trimming 1.14 1.32 table 18. ultra low-power voltage regulator electrical characteristics symbol c parameter conditions min max unit specid t j sr d junction temperature ? ?40 140 c d5.2 i reg cc t current consumption reference included, @ 55 c no load @ full load ? 2 100 a d5.3 i l cc t output current capacity dc load current ? 5 ma d5.4 v dd12 cc d output voltage (value @ i l = 0 @ 27c) pre-trimming sigma < 7 mv ? 1.33 v d5.5 p post-trimming 1.14 1.32
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 73 4.7.3 low voltage domain power consumption table 20 provides dc electrical characteristic s for significant application modes. th ese values are indi cative values; actual consumption depends on the application. table 19. low voltage monitor electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3v 10% / 5.0v 10%, t a = ?40 to 105c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit specid min typ max v porh cc c power-on reset threshold t a = 25c, after trimming 1.5 ? 2.7 v d5.11 v lv d h v3 h cc c lvdhv3 low voltage detector high threshold ? ? 2.8 d5.12 v lv d h v3 l cc c lvdhv3 low voltage detector low threshold 2.7 ? ? d5.13 v lv d h v5 h cc c lvdhv5 low voltage detector high threshold ? ? 4.37 d5.14 v lv d h v5 l cc c lvdhv5 low voltage detector low threshold 4.2 ? ? d5.15 v lv d lv c o r h cc c lvdlvcor low voltage detector high threshold ? ? 1.185 d5.16 v lv d lv c o r l cc c lvdlvcor low voltage detector low threshold 1.095 ? ? d5.17 table 20. dc electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max i ddmax 2 cc d run mode maximum average current ? ? ? 250 276.63 3 ma i ddrun 4 cc p run mode typical average current 5 f cpu = 125 mhz, dual display drive with external dram, 416 tepbga package option only ??275?ma f cpu = 125 mhz, single display drive, no external dram, 176 lqfp / 208 lqfp package options ??240? i ddhalt cc c halt mode current 6 slow internal rc oscillator (128 khz) running t a = 25 o c ? 17.5 21.5 ma pt b = 105 o c ? 35 43.5 i ddstop cc d stop mode current 7 slow internal rc oscillator (128 khz) running t a = ?40 o c?645 ? ? a dt a = 0 o c ? 1100 ? pt a = 25 o c ? 1531 1615 dt a = 55 o c?3.8?ma dt a = 85 o c?9.7? pt a = 105 o c ? 17.67 18.46
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 74 i ddstdby2 cc d standby2 mode current 8 (64k sram on) sxosc (32 khz 9 ) on and rtc running t a = ?40 o c?470 ? ? a dt a = 0 o c?480? pt a = 25 o c ? 481 490 dt a = 55 o c?525? dt a = 85 o c?650? pt a = 105 o c ? 870 910 cc d sxosc (32 khz) and rtc off t a = ?40 o c63? ? a dt a = 0 o c85? pt a = 25 o c 93 100 dt a = 55 o c95? dt a = 85 o c190? pt a = 105 o c 390 430 i ddstdby1 cc d standby1 mode current (8k sram on) 10 sxosc (32khz) on and rtc running t a = ?40 o c?415 ? ? a dt a = 0 o c?422? pt a = 25 o c ? 426 430 dt a = 55 o c?575? dt a = 85 o c?680? pt a = 105 o c ? 810 915 cc d sxosc (32 khz) and rtc off t a = ?40 o c20? ? a dt a = 0 o c22? pt a = 25 o c2945 dt a = 55 o c47? dt a = 85 o c118? pt a = 105 o c 236 310 1 v dd = 3.0 v to 5.5 v, t a = ?40 to 105 c, unless otherwise specified. 2 i ddmax is composed of the current consumption on all supplies (v dd12 , v dde_a , v dde_b , v dda , v ddr , v ddm , v ddpll , and v dd_dr ). it does not include current consumption linked to i/os toggling which is highly dependent on the application. the given value is thought to be a worst case value with all peri pherals running, and code fetched from code flash while modify operation on-going on data flash. it is to be noticed that this value can be significantly reduced by application; switch-off n ot used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from ram most used functions, use low power mode when possible. 3 higher current may be sinked by device during power-up and standby exit. please refer to inrush current in ta b l e 2 1 . 4 run current measured with typical applic ation and accesses on both flash and ram. 5 data and code flash in normal power. code fetched from ram: dcus running with 20mhz pixel clock, quadspi fetching data at 80mhz, gpu accessing internal sram and external dram, dma, rle, and viu active, serial ips can and lin in loop back mode, dspi as master, pll as system clock (4 x multip lier) peripherals on (emios/a dc/smd/ssd/sgm) and running at max frequency, periodic sw/wdg timer reset enabled. table 20. dc electrical characteristics (continued) symbol c parameter conditions 1 value 2 unit min typ max
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 75 4.8 dc electrical specifications 4.8.1 dc specification for cmos 090lp2 library @ vdde = 3.3 v note these pad specifications are applicable for pads in the digital segment only. see the ?gpio power bank supplies and functionality? table in the ?voltage regulators and power supplies? chapter of the reference manual for details. 6 flash in low power. rcosc 128 khz and rcosc 16 mhz on. 10 mhz xtal clock. flexcan: instances: 0, 1on (clocked but no reception or transmission), linflex: instances 0, 1, 2 on (clocked but no reception or transmission). emios: instance: 0, 1 on - 16 channels on with pwm20k hz. dspi: instance : 0 (clocked but no communication). dcus, tcon, viu, gpu clock gated, rtc/api on.pit on. stm on. adc on but not converting. 7 no clock, rc 16mhz off, rci 128 khz on, pll off, hpvreg off, ulpvreg/lpvreg on. all possible peripherals off and clock gated. flash in power down mode. 8 ulpreg on, hp/lpvreg off, 64 kb ram on, device configured for minimum consumption, all possible modules switched off. 9 32 khz oscillator operates at 32,768 hz. 10 ulpreg on, hp/lpvreg off, 8 kb ram on, device configured for minimum consumption, all possible modules switched off. table 21. dc electrical specifications symbol c parameter condition value unit specid min max vdd sr p core supply voltage ? 1.08 1.47 v d9.1 vdde sr p i/o supply voltage ? 3.0 3.6 v d9.2 vdd33 sr p i/o pre-driver supply voltage ? 3.0 3.6 v d9.3 vih_c sr p cmos input buffer high voltage with hysteresis enabled 0.65 ? vdde vdde + 0.3 v d9.4 with hysteresis disabled 0.55 ? vdde vdde + 0.3 vil_c sr p cmos input buffer low voltage with hysteresis enabled vss ? 0.3 0.35 ? vdde v d9.5 with hysteresis disabled vss ? 0.3 0.40 ? vdde vhys_c sr t cmos input buffer hysteresis ? 0.1 ? vdde ? v d9.6 vih_fod_h sr p 5 v tolerant cmos input buffer high voltage with hysteresis enabled 0.65 ? vdd33 vdd33 + 0.3 v d9.7 vil_fod_h sr p 5 v tolerant cmos input buffer low voltage with hysteresis enabled vss ? 0.3 0.35 ? vdd33 v d9.8 iact_s sr t selectable weak pullup/pulldown current ? 25 150 ? ad9.9 iinact_d sr p digital pad input leakage current weak pull inactive ?2.5 2.5 ? a d9.10 iinact_a sr p analog pad input leakage current weak pull inactive ?150 150 ? a d9.11 voh sr p output high voltage ? 0.8 ? vdde ? v d9.12
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 76 vol sr p output low voltage ? ? 0.2 ? vdde v d9.13 voh_pci sr p pci output high voltage ? 0.9 ? vdde ? v d9.14 vol_pci sr p pci output low voltage ? ? 0.1 ? vdde v d9.15 vol_fod_h sr p fast open-drain output low voltage iol_fod_h = 10 ma ? 0.2 ? vdd33 d9.16 table 22. drive current, vdde=3.3 v (10%) pad c drive mode minimum ioh (ma) 1 1 ioh is defined as the current sourced by the pad to drive the output to voh. minimum iol (ma) 2 2 iol is defined as the current sunk by the pad to drive the output to vol. pad_fc c 00 16.1 24 01 31.8 47.9 10 47.2 70.6 11 77 114.5 pad_msr p all 61.9 83.6 pad_ssr p all 61.9 83.6 table 23. supply leakage pad c vdd vdde (typ/max) vdd33 (typ/max) pad_fc d 90 ? a3na / 4 ? a 1 na / 30 ? a pad_msr ? ? ? pad_ssr ? ? ? table 21. dc electrical specifications (continued) symbol c parameter condition value unit specid min max
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 77 4.8.2 dc specification for cmos 090lp2fg library @ vdde = 5.0 v note these pad specifications are applicable for pads in the analog segment only. see the ?gpio power bank supplies and functionality? table in the ?voltage regulators and power supplies? chapter of the reference manual for details. table 24. dc electrical specifications symbol c parameter condition value unit specid min max vdd sr p core supply voltage ? 1.08 1.32 v d9.17 vdde sr p i/o supply voltage ? 4.5 5.5 v d9.18 vdd33 sr p i/o pre-driver supply voltage ? 3.0 3.6 v d9.19 vih_hys sr p cmos input buffer high voltage with hysteresis enabled 0.65 ? vdde vdde + 0.3 v d9.20 vil_hys sr p cmos input buffer low voltage with hysteresis enabled vss ? 0.3 0.35 ? vdde v d9.21 vih sr p cmos input buffer high voltage with hysteresis disabled 0.55 ? vdde vdde + 0.3 v d9.22 vil sr p cmos input buffer low voltage with hysteresis disabled vss ? 0.3 0.40 ? vdde v d9.23 vhys sr t cmos input buffer hysteresis ? 0.1 ? vdde ? v d9.24 pull_ioh sr p weak pullup current ? 35 135 ? a d9.25 pull_iol sr p weak pulldown current ? 35 200 ? a d9.26 iinact_d sr p digital pad input leakage current weak pull inactive ?2.5 2.5 ? a d9.27 iinact_a sr p analog pad input leakage current weak pull inactive ?150 150 ? a d9.28 voh sr p slew rate controlled output high voltage ?0.8 ? vdde ? v d9.29 vol sr p slew rate controlled output low voltage ??0.2 ? vdde v d9.30 voh_ls sr p low swing output pad output high voltage ? 2.64 ? v d9.31 ioh_msr sr c pad_msr_hv ioh ? 11.6 40.7 ma d9.32 iol_msr sr c pad_msr_hv iol ? 17.7 68.2 ma d9.33 ioh_ssr sr c pad_ssr_hv ioh ? 6.0 21.3 ma d9.34 iol_ssr sr c pad_ssr_hv iol ? 9.2 36.3 ma d9.35 ioh_multv_h s sr c pad_multv_hv ioh high swing mode 10 40 ma d9.36 ioh_multv_l s sr c pad_multv_hv ioh low swing mode tbd tbd ma d9.37 iol_multv sr c pad_multv_hv iol high/low swing mode 12 56 ma d9.38
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 78 rtgate sr d pad_tgate_hv input resistance ? 250 800 ? d9.39 pupd_rm sr d pad_pupd_hv resistance mismatch ??5%d9.40 pupd_leak sr d pad_pupd_hv leakage current ? 0.1 75000 pa d9.41 pupd200k sr d pad_pupd_hv 200 k ? resistance ? 130 280 k ? d9.42 pupd100k sr d pad_pupd_hv 100 k ? resistance ? 65 140 k ? d9.43 pupd5k sr d pad_pupd_hv 5 k ? resistance ?1.45.2k ? d9.44 table 25. dc electrical specifications symbol parameter condition value unit specid min max vdd sr core supply voltage ? 1.08 1.32 v d9.45 vdde sr i/o supply voltage ? 3.0 3.6 v d9.46 vdd33 sr i/o pre-driver supply voltage ? 3.0 3.6 v d9.47 vih_hys sr cmos input buffer high voltage with hysteresis enabled 0.65 ? vdde vdde + 0.3 v d9.48 vil_hys sr cmos input buffer low voltage with hysteresis enabled vss ? 0.3 0.35 ? vdde v d9.49 vih sr cmos input buffer high voltage with hysteresis disabled 0.55 ? vdde vdde + 0.3 v d9.50 vil sr cmos input buffer low voltage with hysteresis disabled vss ? 0.3 0.40 ? vdde v d9.51 vhys sr cmos input buffer hysteresis ? 0.1 ? vdde ? v d9.52 pull_ioh sr weak pullup current ? 15 70 ? a d9.53 pull_iol sr weak pulldown current ? 15 95 ? a d9.54 iinact_d sr digital pad input leakage current weak pull inactive ?2.5 2.5 ? a d9.55 iinact_a sr analog pad input leakage current weak pull inactive ?150 150 ? a d9.56 voh sr slew rate controlled output high voltage ?0.8 ? vdde ? v d9.57 vol sr slew rate controlled output low voltage ??0.2 ? vdde v d9.58 table 24. dc electrical specifications (continued) symbol c parameter condition value unit specid min max
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 79 ioh_msr sr pad_msr_hv ioh ? 5.4 21 ma d9.59 iol_msr sr pad_msr_hv iol ? 8.1 38.6 ma d9.60 ioh_ssr sr pad_ssr_hv ioh ? 2.8 11.2 ma d9.61 iol_ssr sr pad_ssr_hv iol ? 4.2 20.6 ma d9.62 ioh_multv_h s sr pad_multv_hv ioh high swing mode ? tbd ma d9.63 iol_multv sr pad_multv_hv iol high/low swing mode ? tbd ma d9.64 rtgate sr pad_tgate_hv input resistance ? 325 1250 ? d9.65 pupd_rm sr pad_pupd_hv resistance mismatch ??5%d9.66 pupd_leak sr pad_pupd_hv leakage current ? 0.1 75000 pa d9.67 pupd200k sr pad_pupd_hv 200 k ? resistance ?130280k ? d9.68 pupd100k sr pad_pupd_hv 100 k ? resistance ?65140k ? d9.69 pupd5k sr pad_pupd_hv 5 k ? resistance ?1.77.7k ? d9.70 table 26. supply leakage pad vdd vdde vdd33 typ max typ max typ max pad_msr_hv 0.818 na 83.7 na 0.81 na 118 na ? ? pad ssr_hv 0.818 na 83.7 na 0.858 na 88.7 na ? ? pad_i_hv 0.307 na 48.4 na 88.2 pa 30 na ? ? biasref_hv ?????? core_v_det_hv 0 0 ? ? 0 0 core_v_det_lp_hv 0 0 ? ? ? ? corner_esdpadcell_hv?????? corner_esdpadcell_id00_hv ?????? corner_esdpadcell_id11_hv ?????? corner_esdpadcell_lp_hv?????? esd_term_35_84_hv ?????? pad_9v_hv 0 0 ? ? ? ? pad_ae_hv ?????? table 25. dc electrical specifications (continued) symbol parameter condition value unit specid min max
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 80 pad_esdspacer_hv ?????? pad_tgate_hv ?????? pad_vdd33_hv ?????? pad_vdde_hv 0 0 ? ? 0 0 pad_vddint3v_hv 0 0 ? ? 0 0 pad_vddint_hv 0 0 ? ? ? ? pad_vss_hv 0 0 ? ? ? ? pad_vsse_hv 0 0 ? ? ? ? pad_vssint3v_hv 0 0 ? ? ? ? pad_vssint_hv 0 0 ? ? ? ? spcr_17_82_hv ?????? spcr_35_84_hv ?????? spcr_71_88_hv ?????? spcr_143_38_hv ?????? spcr_vdde_lvl_hv ?????? table 27. avg idde specifications cell period (ns) load (pf) 1 1 all loads are lumped loads. vdde (v) drive/slew select idde (ma) pad_msr_hv 2 2 average current is for pad configured as output only. use pad_i current for input. 24 50 5.5 11 14 62 50 5.5 01 5.3 317 50 5.5 00 1.1 425 200 5.5 00 3 pad_ssr_hv 2 37 50 5.5 11 9 130 50 5.5 01 2.5 650 50 5.5 00 0.5 840 200 5.5 00 1.5 table 26. supply leakage (continued) pad vdd vdde vdd33 typ max typ max typ max
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 81 4.8.3 dc specification for cmos 090_ddr library @ vdde = 3.3 v 4.8.4 dc specification for cmos 090_ddr library @ vdde = 2.5 v table 28. dc electrical specifications at 3.3 v vdde symbol parameter value unit specid min max vdd sr core supply voltage 1.08 1.32 v d9.71 1.08 1.47 vdde sr i/o supply voltage 3.0 3.6 v d9.72 vdd33 sr i/o pre-driver supply voltage 3.0 3.6 v d9.73 vref sr input reference voltage 1.3 1.7 v d9.74 vtt sr termination voltage vref ? 0.05 vref + 0.05 v d9.75 vih sr input high voltage vref + 0.20 ? v d9.76 vil sr input low voltage ? vref ? 0.2 v d9.77 voh sr output high voltage vtt + 0.8 ? v d9.78 vol sr output low voltage ? vtt ? 0.8 v d9.79 table 29. output drive current @ vdde = 3.3 v (10%) pad c drive mode minimum io h (ma) minimum iol (ma) pad_st_acc p 111 ?16 16 pad_st_dq p 111 ?16 16 pad_st_clk p 111 ?16 16 pad_st p 111 ?16 16 pad_st_odt p 111 ?16 16 pad_st_ck p 111 ?16 16 table 30. dc electrical specifications at 2.5 v vdde symbol c parameter value unit specid min max vdd sr p core supply voltage 1.08 1.32 v d9.80 1.08 1.47 vdde sr p i/o supply voltage 2.3 2.7 v d9.81 vdd33 sr p i/o pre-driver supply voltage 3.0 3.6 v d9.82 vref sr p input reference voltage 0.49 ? vdde 0.51 ? vdde v d9.83 vtt sr p termination voltage vref ? 0.04 vref + 0.04 v d9.84
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 82 4.8.5 dc specification for cmos 090_ddr library @ vdde = 1.8 v vih sr p input high voltage vref + 0.15 ? v d9.85 vil sr p input low voltage ? vref ? 0.15 v d9.86 voh sr p output high voltage vtt + 0.81 ? v d9.87 vol sr p output low voltage ? vtt ? 0.81 v d9.88 table 31. output drive current @ vdde = 2.5 v (200mv) pad c drive mode minimum ioh (m a) minimum iol (ma) libraries pad_st_acc p 011 ?16.2 16.2 6mddr pad_st_dq p 011 ?16.2 16.2 6mddr pad_st_ck p 011 ?16.2 16.2 6mddr table 32. dc electrical specifications for 1.8 v vdde symbol c parameter value unit specid min max vdd sr p core supply voltage 1.08 1.32 v d9.89 1.08 1.47 vdde sr p i/o supply voltage 1.7 1.9 v d9.90 vdd33 sr p i/o pre-driver supply voltage 3.0 3.6 v d9.91 vref sr p input reference voltage 0.49 ? vdde 0.51 ? vdde v d9.92 vtt sr p termination voltage vref ? 0.04 vref + 0.04 v d9.93 vih sr p input high voltage vref + 0.125 ? v d9.94 vil sr p input low voltage ? vref ? 0.125 v d9.95 voh sr p output high voltage vtt + 0.81 ? v d9.96 vol sr p output low voltage ? vtt ? 0.81 v d9.97 table 33. output drive current @ vdde = 1.8 v (100mv) pad drive mode minimum ioh (ma) minimum iol (ma) libraries pad_st_acc p 000 ?3.57 3.57 6mddr 001 ?7.84 7.84 010 ?5.36 5.36 110 ?13.4 13.4 table 30. dc electrical specifications at 2.5 v vdde (continued) symbol c parameter value unit specid min max
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 83 pad_st_dq p 000 ?3.57 3.57 6mddr 001 ?7.84 7.84 010 ?5.36 5.36 110 ?13.4 13.4 pad_st_clk p 000 ?3.57 3.57 6mddr 001 ?7.84 7.84 010 ?5.36 5.36 110 ?13.4 13.4 table 34. odt dc electrical characteristics symbol c parameter condition value unit specid min typ max rtt sr c effective impedance value PXD20 supports only 150 ohm termination and that can be enabled by enabling any bit of the termination control register (all of them are or?ed). 120 150 180 ? d9.98 table 35. core_v_det_odt and core_v_det33_odt specifications vdde c vdd vtrip max (v) vtrip min hysteresis min (v) 3.5 c rising 0.79 0.44 0.07 c falling 0.56 0 1.62 c rising 0.65 0.3 0.16 c falling 0.33 0 rising c 0.0 1.40 0.3 ? table 33. output drive current @ vdde = 1.8 v (100mv) (continued) pad drive mode minimum ioh (ma) minimum iol (ma) libraries
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 84 4.9 reset electrical characteristics the device implements a dedicated bidirectional reset pin. figure 9. start-up reset requirements figure 10. noise filtering on reset signal v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 85 table 36. reset electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3v 10% / 5.0v 10%, t a = ?40 to +105 o c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit specid min typ max v ih sr p input high level cmos schmitt trigger ?0.65v dd ?v dd +0.4 v d8.1 v il sr p input low level cmos schmitt trigger ? ?0.4 ? 0.35 v dd vd8.2 v hys cc 3 3 data based on characterization results, not tested in production d input hysteresis cmos schmitt trigger ?0.1v dd ?? vd8.3 v ol cc 4 4 guaranteed by design simulation. p output low level push pull, i ol = 2ma, v dd = 5.0v 10%, ipp_hve = 0 (recommended) ??0.1v dd vd8.4 dpush pull, i ol = 1ma, v dd = 5.0v 10%, ipp_hve = 1 5 5 this is a transient configuration during power-up, up to the end of reset phase2 (refer to rgm module section of the reference manual). ??0.1v dd cpush pull, i ol = 1ma, v dd = 3.3v 10%, ipp_hve = 1 (recommended) ??0.5 t tr cc 4 t output transition time output pin 6 medium configuration 6 c l calculation should include device and package capacitance (c pkg < 5pf). c l = 25pf, v dd = 5.0v 10%, ipp_hve = 0 ? ? 10 ns d8.5 c l = 50pf, v dd = 5.0v 10%, ipp_hve = 0 ?? 20 c l = 100pf, v dd = 5.0v 10%, ipp_hve = 0 ?? 40 c l = 25pf, v dd = 3.3v 10%, ipp_hve = 1 ?? 12 c l = 50pf, v dd = 3.3v 10%, ipp_hve = 1 ?? 25 c l = 100pf, v dd = 3.3v 10%, ipp_hve = 1 ?? 40 w frst sr p reset input filtered pulse ? ? ? 70 ns d8.6 w nfrst sr p reset input not filtered pulse ? 400 ? ? ns d8.7 |i wpu |cc 4 p weak pullup current absolute val- ue ?10??ad8.8
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 86 4.10 fast external crystal o scillator (4?16 mhz) electrical characteristics this device implements the fast external oscillator (fxosc) using a low power loop controlled pierce oscillator (lcp) configuration. table 37. fast external crystal oscillator electrical characteristics symbol parameter conditions value unit specid min typ max f osc c crystal oscillator range loop controlled pierce 4.0 ? 16 mhz o9.1 i osc p startup current ? 100 ? a o9.2 ? t uposc c oscillator start-up time loop controlled pierce 4 1 1 f osc = 4 mhz, c = 22 pf 50 2 2 maximum value is for extreme cases using high q, low frequency crystals ms o9.3 t cqout d clock quality check time-out ? 0.45 ? 2.5 s o9.4 f cmfa d clock monitor failure assert frequency ? 200 400 800 khz o9.5 f ext d external square wave input frequency 2 ? 2.0 ? 50 mhz o9.6 t extl d external square wave pulse width low ? 9.5 ? ? ns o9.7 t exth d external square wave pulse width high ? 9.5 ? ? ns o9.8 t extr d external square wave rise time ? ? ? 1 ns o9.9 t extf d external square wave fall time ? ? ? 1 ns o9.10 c in d input capacitance extal and xtal pins ? 7 ? pf o9.11 v ih,extal p extal pin input high voltage 2 ?0.75 ? v ddpll ?? vo9.12 t??v ddpll +0.3 v il,extal p extal pin input low voltage 2 ???0.25 ? v ddpll vo9.13 tv sspll ?0.3 ?? v hys,extal c extal pin input hysteresis 2 ? 180 ? mv o9.14 v pp,extal c extal pin oscillation amplitude loop controlled pierce ? 1.0 ? v o9.15
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 87 4.11 slow external crystal oscillator (32 khz) electrical characteristics the device provides a slow external osci llator/resonator driver (sxosc). the 32 khz oscillator operates at 32,768 hz. figure 11. crystal oscillator and resonator connection scheme note pc[14]/pc[15] must not be directly used to drive ex ternal circuits. figure 12. slow external crystal oscillator electrical characteristics c y c x crystal pc[14] pc[15] r f resonator pc[14] pc[15] device device v dd t xosclpsu v ddmin v xtal v xosclp valid internal clock 90% 10% 1/f xosclp
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 88 4.12 fmpll electrical characteristics the device provides a frequency-modulated phase-locked loop (fmpll ) module to generate a fast system clock from the fast external oscillator driver. table 38. slow external crystal oscillator electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to +105 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit specid min typ max f xosclp sr c oscillator frequency 32 ? 40 khz o10.1 v xosclp cc 3 3 granted by device validation c oscillation amplitude v dda =3.3v ? 10%, v dde_a =3.3v ? 10% 1.12 1.33 1.74 v o10.2 v dda =5.0v ? 10%, v dde_a =5.0v ? 10% 1.12 1.37 1.74 i xosclp cc 3 d oscillator consumption ? ? ? 5 a o10.3 t xosclps u cc 3 d oscillator start-up time ? ? ? 2 s o10.4 v ih sr c input high level cmos schmitt trigger oscillator bypass mode 0.65v dda 0.65v dde_a ?v dda +0.4 v dde_a +0.4 v o10.5 v il sr c input low level cmos schmitt trigger oscillator bypass mode v ss ?0.4 ? 0.35v dda 0.35v dde_a v o10.6 table 39. fmpll electrical characteristics symbol c parameter conditions 1 1 v ddpll = 1.2 v 10%, t a = ?40 to 105 c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit specid min typ max f pllin sr t pll reference clock 3 3 pllin clock retrieved directly from xoschs clock. input characteristics are granted when oscillator is used in functional mode. when bypass mode is used, oscillator input clock should verify f pllin and ? pllin . ? 4 ? 120 mhz o11.1 ? pllin sr t pll reference clock duty cycle 3 ? 47.5 ? 52.5 % o11.2 f pllout cc 4 t pll output clock frequency ? 15 ? 250 5 mhz o11.3 f cpu cc 4 t system clock frequency ? ? ? 125 6 mhz o11.4 t lock cc 4 t pll lock time stable oscillator (f pllin = 10 mhz) ? ? 100 s o11.5 ? t pkjit cc 4 t pll jitter f pllout (phi i.e. fmpll o/p) = 15.625 mhz @ 10 mhz resonator ?509 ? 509 ps o11.6 ? t ltjit cc 4 t pll long term jitter f pllin = 10 mhz (resonator) ?2.4 ? 2.4 ns o11.7 i pll cc 7 d current consumption (normal mode for analog supply) t a = 25c ? ? 500 a o11.8
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 89 4.13 fast internal rc oscillator (16 mhz) electrical characteristics the device provides a fast internal rc oscillator (firc). this is used as the default clock at the power-up of the device. 4.14 slow internal rc oscillator (128 khz) electrical characteristics the device provides a slow internal rc oscillator (sirc). this can be used as the reference clock for the rtc module. 4 data based on device simulation. 5 2x sys clock required for generation of ddr timing. 6 f cpu of 125 mhz can be achieved only at temperatur es up to 105 c with a maximum fm depth of 2%. 7 data based on characterization results, not tested in production table 40. fast internal oscillator electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 105 c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit specid min typ max f rcm cc 3 3 guaranteed by device simulation, not tested in production p rc oscillator high frequency t a = 25 c, trimmed ? 16 ? mhz o12.1 i rcmrun cc 3 d rc oscillator high frequency current in run- ning mode t a = 25 c, trimmed ? ? 200 a o12.2 i rcmpwd cc 3 d rc oscillator high frequency current in power down mode t a = 25 c ? ? 10 a o12.3 ? rcmvar cc 4 4 guaranteed by device characterization, not tested in production c rc oscillator variation in temperature and supply with respect to f rc at t a = 55 c in high-frequency configuration ? ?5 ? +5 % o12.5 table 41. slow internal rc oscillator electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to +105 c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit specid min typ max f rcl cc 3 3 guaranteed by device simulation, not tested in production p rc oscillator low frequency t a = 25 c, trimmed ? 128 ? khz o13.1 i rcl cc 3 d rc oscillator low frequency current t a = 25 c, trimmed ? ? 5 a o13.2 ? rcltri m cc 3 c rc oscillator precision after trimming of f rcl t a = 25 c ?2 ? +2 % o13.3 ? rclvar 3 cc 3 c rc oscillator variation in temperature and supply with respect to f rc at t a = 55 c in high frequency configuration high frequency config- uration ?10 ? +10 % o13.4
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 90 4.15 flash memory electrical characteristics table 42. program and erase specifications symbol c parameter min value typical value 1 1 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. initial max 2 2 initial factory condition: < 100 program/er ase cycles, 25 c, typical supply voltage. max 3 3 the maximum program & erase times occur after the specified number of program/ erase cycles. these maximum values are characterized but not guaranteed. unit specid t dwprogram c double word (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. ?22500 ? sd14.1 t 16kpperase c 16 kb block pre-program and erase time ? 500 5000 ms d14.2 t 32kpperase c 32 kb block pre-program and erase time ? 600 5000 ms d14.3 t 128kpperase c 128 kb block pre-program and erase time ? 1300 7500 ms d14.4 table 43. flash module life symbol c parameter conditions value unit specid min typ p/e c number of program/erase cycles per block for 16 kb, 48kb and 64kb blocks, across full operating temperature range (tj) ? 100,000 ? p/e cycles d14.5 p/e c number of program/erase cycles per block for 128kb and 256kb blocks, across full operating temperature range (tj) ? 1, 000 100,000 p/e cycles d14.6 data retention c minimum data retention at 85 c average ambient temperature 1 1 ambient temperature averaged over duration of applicati on, not to exceed recommended product operating temperature range. blocks with 0 ? 1,000 p/e cycles 20 ? years d14.8 blocks with 1,001 ? 10,000 p/e cycles 10 ? years blocks with 10,001 ? 100,000 p/e cycles 5 ? years
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 91 4.16 adc parameters the device provides a 10-bit succe ssive approximation register (sar ) analog to digital converter. figure 13. adc characteristics and error definitions 4.16.1 input impedance and adc accuracy in the following analysis, the input circuit corres ponding to the precise ch annels is considered. to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacito r with good high frequency characteristics at the input pin of th e device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenuat ing the noise present on the input pin; furthermore, it sourc es charge during the sampling phase, when the anal og signal source is a high-impedance source. (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 1 lsb ideal = v dda / 1024
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 92 a real filter can typically be obtained by using a series re sistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the value of source impedance of the tr ansducer or circuit supp lying the analog signal to be measured. the filter at the input pins mu st be designed taking into account the d ynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contri butor is represented by the charge shari ng effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive p ath to ground. for instance, assuming a conversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330 k ? is obtained (r eq = 1 / (fc c s ), where fc represents the conversion rate at the consider ed channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s + r f + r l + r sw + r ad , the external circuit must be designed to respect the equation 5 : eqn. 5 equation 5 generates a constraint for external network design, in pa rticular on resistive path. in ternal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 14. input equivalent circuit (precise channels) v a r s r f r l r sw r ad +++ + r eq --------------------------------------------------------------------------- ? 1 2 -- -lsb ? r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 93 figure 15. input equivalent circuit (extended channels) a second aspect involving the capacitance network sha ll be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit reported in figure 14 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch close). figure 16. transient behavior during sampling phase in particular two different transient periods can be distinguished: ? a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is eqn. 6 equation 6 can again be simplifi ed considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: r f c f r s r l r sw1 c p3 c s v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw channel selection switch impedance (two contributions r sw1 and r sw2 ) r ad sampling switch impedance c p pin capacitance (three contributions, c p1 , c p2 and c p3 ) c s sampling capacitance c p1 r ad channel selection v a c p2 extended r sw2 switch v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 ) ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- ?
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 94 eqn. 7 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 8 : eqn. 8 ? a second charge transfer involves also c f (that is typically bigger than the on- chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: eqn. 9 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: eqn. 10 of course, r l shall be sized also according to the current limitation constr aints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer tr ansient) will be mu ch higher than v a1 . equation 11 must be respected (charge balance assuming now c s already charged at v a1 ): eqn. 11 the two transients above are not influenced by th e voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to comp ensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is ty pically designed to act as anti-aliasing. figure 17. spectral representation of input signal ? 1 r sw r ad + ?? ? c s t s ? ? v a1 c s c p1 c p2 ++ ?? ? v a c p1 c p2 + ?? ? = ? 2 r l ? c s c p1 c p2 ++ ?? ? 10 ? 2 ? 10 r l c s c p1 c p2 ++ ?? ? ? =t s ? v a2 c s c p1 c p2 c f +++ ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? = f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 ?? f c (nyquist) f f ? f 0 (anti-aliasing filtering condition) t c ?? 2 r f c f (conversion rate vs. filter pole) noise
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 95 calling f 0 the bandwidth of the source signal (and as a conseque nce the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant ti me of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continu ous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accur acy error due to the voltag e drop on c s ; from the two charge balance equations above, it is simple to derive equation 12 between the ideal and real sampled voltage on c s : eqn. 12 from this formula, in the worst case (when v a is maximum, that is fo r instance 5v), assuming to accept a maximum error of half a count, a constraint is evident on c f value: eqn. 13 4.16.2 adc electrical characteristics table 44. adc electrical characteristics symbol c parameter conditions 1 value 2 unit specid min typ max v ssa sr d voltage on vssa (adc reference) pin with re- spect to ground (v ss ) 3 ? ?0.1 ? 0.1 v d15.1 v dda sr d voltage on vdda pin (adc reference) with re- spect to ground (v ss ) ?v dde_a ?0. 1 ?v dde_a +0.1 v d15.2 v ainx sr d analog input voltage 4 ?v ssa ?0.1 ? v dda +0.1 v d15.3 f adc sr d adc analog frequency ? 6? 32 mhz d15.4 t adc_pu sr d adc power up delay ? ? 1.5 s d15.5 t adc_s cc 5 t sample time 6 f adc = 32 mhz, adc_conf_sample_input = 17 0.5 ? s d15.6 f adc = 6 mhz, adc_conf_sample_input = 127 ?21 t adc_c cc 5 t conversion time 7 f adc = 32 mhz, adc_conf_comp = 2 0.625 ? ? s d15.7 v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? ?
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 96 c s cc 5 d adc input sampling capacitance ??? 3 pf d15.8 c p1 cc 5 d adc input pin capacitance 1 ??? 3 pf d15.9 c p2 cc 5 d adc input pin capacitance 2 ??? 1 pf d15.10 c p3 cc 5 d adc input pin capacitance 3 ??? 1 pf d15.11 r sw1 cc 5 d internal resistance of analog source ??? 3 k ? d15.12 r sw2 cc 5 d internal resistance of analog source ??? 2 k ? d15.13 r ad cc 5 d internal resistance of analog source ??? 0.1 k ? d15.14 i inj sr t input current injection current injection on one adc input, different from the converted one ?10 ? 10 ma d15.15 inl cc 5 p integral non linearity no overload ?1.5 ? 1.5 lsb d15.16 dnl cc 5 p differential non linearity no overload ?1.0 ? 1.0 lsb d15.17 ofs cc 5 t offset error after offset cancellation ? 0.5 ? lsb d15.18 gne cc 5 t gain error ? ? 0.6 ? lsb d15.19 tuex cc t total unadjusted error for extended channel no overload ?3 ? 3 lsb d15.21 tuep cc 5 t total unadjusted error for precise channels, input only pins no overload ?2 ? 2 lsb d15.22 overload conditions on adjacent channel ?? lsb tuex cc 5 t total unadjusted error for extended channel, no overload ?3 ? 3 lsb d15.23 overload conditions on adjacent channel ?? ? lsb 1 v dda = 3.3 v 10% / 5.0 v 10%, t a = ?40 to +105 c, unless otherwise specified. 2 all values need to be confirmed during device validation. 3 analog and digital v ss must be common (to be tied together externally). 4 v ainx may exceed v ssa and v dda limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3ff 5 guaranteed by design 6 during the sample time the input capacitance c s can be charged/discharged by the exte rnal source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t adc_s . after the end of the sample time t adc_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc_s depend on programming. 7 this parameter does not include the sample time t adc_s , but only the time for determining the digital result and the time to load the result?s register with the conversion result. table 44. adc electrical characteristics (continued) symbol c parameter conditions 1 value 2 unit specid min typ max
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 97 4.17 ac specifications 4.17.1 ac specification for cmos090lp2 library @ vdde = 3.3 v table 45. functional pad type ac specifications name c prop. delay (ns) l>h / h>l 1 1 l>h signifies low-to-high propagation delay and h>l signifies high-to-low propagation delay. rise/fall edge (ns) drive load (pf) drive/slew rate select minmaxminmax msb, lsb pad_ssr c ? 4.5 / 4.5 ? 2.2 / 2.2 50 11 2 2 can be used on the tester. ? 8 / 8 ? 6 / 6 200 ? 45 / 45 ? 22 / 22 50 10 ? 60 / 60 ? 28 / 28 200 ? 90 / 90 ? 42 / 42 50 01 ? 110 / 110 ? 50 / 50 200 ? 430 / 430 ? 210 / 210 50 00 ? 480 / 480 ? 220 / 220 200 pad_fc c ? 2.5 / 2.5 ? 1.2 / 1.2 10 00 ? 2.5 / 2.5 ? 1.2 / 1.2 20 01 ? 2.5 / 2.5 ? 1.2 / 1.2 30 10 ? 2.5 / 2.5 ? 1.2 / 1.2 50 11 2 pad_msr c ? 4.0 / 4.5 ? 1.02 / 1.4 50 11 2 ? 7.3 / 8.3 ? 3.5 / 4.2 200 ? 24 / 22 ? 9.1 / 10.3 50 10 ? 33 / 31 ? 14 / 15 200 ? 49 / 44 ? 18 / 21 50 01 ? 60 / 53 ? 24 / 25 200 ? 332 / 302 ? 126 / 151 50 00 ? 362 / 325 ? 136 / 158 200
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 98 4.17.2 ac specification for cmos090lp2fg library @ vdde = 5.0 v 4.17.3 ac specification for cmos090lp2fg library @ vdde = 3.3 v table 46. functional pad type ac specifications name c prop. delay (ns) l>h / h>l 1 1 l>h signifies low-to-high propagation delay an d h>l signifies high-to-low propagation delay. rise/fall edge (ns) drive load (pf) drive/slew rate select minmaxminmax msb, lsb pad_msr_hv 2 2 for input buffer timing, look at pad_i_hv. c 4.6 / 3.7 12 / 12 2.2 / 2.2 5.3 / 5.9 50 11 3 3 can be used on the tester. 13 / 10 32 / 32 9 / 9 22 / 22 200 n/a 10 4 4 this drive select value is not supported. if selected, it will be approximately equal to 11. 12 / 13 28 / 34 5.6 / 6 12 / 15 50 01 23 / 23 52 / 59 11 / 14 28 / 31 200 69 / 71 152 / 165 34 / 35 70 / 74 50 00 95 / 90 205 / 220 44 / 51 96 / 96 200 pad_ssr_hv 2 c 7.3 / 5.7 19 / 18 4.4 / 4.3 10 / 11 50 11 3 24 / 19 58 / 58 17 / 15 40 / 42 200 n/a 10 4 26 / 27 61 / 69 13 / 13 30 / 34 50 01 49 / 45 115 / 115 27 / 23 61 / 61 200 137 / 142 320 / 330 72 / 74 156 / 164 50 00 182 / 172 420 / 420 90 / 85 200 / 200 200 pad_i_hv c 0.5 / 0.5 1.9 / 1.9 0.3 / 0.3 1.5 / 1.5 0.5 n/a table 47. functional pad ac type specifications name prop. delay (ns) l>h / h>l rise/fall edge (ns) drive load (pf) drive/slew rate select min max min max msb, lsb pad_msr_hv 5.8 / 4.4 18 / 17 2.7 / 2.1 7.6 / 8.5 50 11 16 / 13 46 / 49 11.2 / 8.6 30 / 34 200 n/a 10 14 / 16 37 / 45 6.5 / 6.7 15.5 / 19 50 01 27 / 27 69 / 82 15 / 13 38 / 43 200 83 / 86 200 / 210 38 / 38 86 / 86 50 00 113 / 109 270 / 285 53 / 46 120 / 120 200
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 99 4.17.4 pad ac specifications (3.3 v, pad3v5v = 1) pad_ssr_hv 9.2 / 6.9 27 / 28 5.5 / 4.1 15 / 17 50 11 30 / 23 81 / 87 21 / 16 57 / 63 200 n/a 10 31 / 31 80 / 90 15.4 / 15.4 38 / 42 50 01 58 / 52 144 / 155 32 / 26 82 / 85 200 162 / 168 415 / 415 80 / 82 190 / 190 50 00 216 / 205 533 / 540 106 / 95 250 / 250 200 pad_i_hv 0.5 / 0.5 3 / 3 0.4 / 0.4 1.5 / 1.5 0.5 n/a table 48. pad ac specifications (3.3 v, pad3v5v = 1) 1 1 propagation delay from v dd /2 of internal signal to pchannel/nchannel on condition no. pad tswitchon 1 (ns) rise/fall 2 (ns) 2 slope at rising/falling edge frequency (mhz) current slew (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max 1 slow 3 ? 40 4 ? 40 ? ? 4 0.01 ? 2 25 3?406?50??20.01?2 50 3 ? 40 10 ? 75 ? ? 2 0.01 ? 2 100 3 ? 40 14 ? 100 ? ? 2 0.01 ? 2 200 2 medium 1 ?15 2 ?12??402.5? 7 25 1 ? 15 4 ? 25 ? ? 20 2.5 ? 7 50 1 ? 15 8 ? 40 ? ? 13 2.5 ? 7 100 1 ? 15 14 ? 70 ? ? 7 2.5 ? 7 200 3 fast 1 ? 6 1 ? 4 ??72 3 ?40 25 1?61.5?7??553?40 50 1 ? 6 3 ?12??40 3 ?40 100 1 ? 6 5 ?18??25 3 ?40 200 4pull up/down (3.6 v max) ?????7500?????? 50 parameter classification dcccn/a table 47. functional pad ac type specifications (continued) name prop. delay (ns) l>h / h>l rise/fall edge (ns) drive load (pf) drive/slew rate select min max min max msb, lsb
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 100 4.17.5 ac specification for cmos 090_ddr library @ vdde = 3.3 v 4.17.6 ac specification for cmos 090_ddr library @ vdde = 2.5 v table 49. ac specifications at 3.3 v vdde name c prop. delay (ns) l>h / h>l rise/fall edge (ns) drive load (pf) drive/slew rate select libraries min max min max msb, lsb pad_st_acc c 1.4/1.4 2.4/2.4 3.1/2.5 5.6/5.4 5 111 6mddr 1.7/1.7 2.7/2.7 0.9/1.1 1.7/2.0 20 pad_st_dq c 1.4/1.4 2.4/2.4 3.1/2.5 5.6/5.4 5 111 6mddr 1.7/1.7 2.7/2.7 0.9/1.1 1.7/2.0 20 pad_st_clk c 1.4/1.4 2.4/2.4 3.1/2.5 5.7/5.7 5 111 6mddr 1.6/1.6 2.6/2.6 1.1/1.3 2.3/2.3 20 table 50. ac specifications at 2.5 v vdde name c prop. delay (ns) l>h / h>l rise/fall edge (ns) drive load (pf) drive/slew rate select libraries min max min max msb, lsb pad_st_acc c 1.4/1.5 2.5/2.4 2.1/2.1 4.3/4.1 5 011 6mddr 1.7/1.7 2.8/2.7 0.6/0.7 1.1/1.3 20 pad_st_dq c 1.4/1.5 2.5/2.4 2.1/2.1 4.3/4.1 5 011 6mddr 1.7/1.7 2.8/2.7 0.6/0.7 1.1/1.3 20 pad_st_clk c 1.4/1.4 2.4/2.4 2.1/2.1 4.4/4.1 5 011 6mddr 1.1/1.6 2.7/2.7 0.6/0.7 1.6/1.8 20
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 101 4.17.7 ac specification for cmos 090_ddr library @ vdde = 1.8 v table 51. ac electrical specifications at 1.8 v vdd name c prop. delay (ns) l>h / h>l rise/fall edge (ns) drive load (pf) drive/slew rate select libraries minmaxminmax msb, lsb pad_st_acc c 1.4/1.4 2.4/2. 4 0.6/1.0 2.7/2.6 5 000 6mddr 1.7/1.7 2.8/2.7 0.2/0.4 0.5/0.6 20 1.4/1.5 2.4/2.5 1.1/1.1 3.0/2.7 5 001 1.7/1.7 2.8/2.8 0.4/0.4 0.7/0.7 20 1.4/1.5 2.4/2.4 1.0/1.1 2.9/2.7 5 010 1.7/1.7 2.8/2.7 0.3/0.4 0.6/0.7 20 1.4/1.5 2.5/2.5 1.5/1.1 3.1/2.6 5 110 1.7/1.8 2.8/2.8 0.4/0.4 0.7/0.6 20 pad_st_dq c 1.4/1.4 2.4/2. 4 0.6/1.0 2.7/2.6 5 000 6mddr 1.7/1.7 2.8/2.7 0.2/0.4 0.5/0.6 20 1.4/1.5 2.4/2.5 1.1/1.1 3.0/2.7 5 001 1.7/1.7 2.8/2.8 0.4/0.4 0.7/0.7 20 1.4/1.5 2.4/2.4 1.0/1.1 2.9/2.7 5 010 1.7/1.7 2.8/2.7 0.3/0.4 0.6/0.7 20 1.4/1.5 2.5/2.5 1.5/1.1 3.1/2.6 5 110 1.7/1.8 2.8/2.8 0.4/0.4 0.7/0.6 20 pad_st_clk c 1.4/1.4 2.4/2. 4 0.4/0.6 2.7/2.7 5 000 6mddr 1.6/1.6 2.7/2.7 0.7/0.9 1.8/3.4 20 1.4/1.4 2.4/2.4 1.1/1.1 3.0/2.8 5 001 1.7/1.7 2.7/2.7 0.3/0.4 1.0/1.1 20 1.4/1.4 2.4/2.4 0.9/1.1 3.0/2.8 5 010 1.6/1.6 2.7/2.7 0.3/0.4 0.9/1.0 20 1.4/1.5 2.5/2.5 1.5/1.2 3.2/2.6 5 110 1.7/1.8 2.7/2.7 0.4/0.4 1.1/1.2 20
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 102 4.18 ac timing 4.18.1 ieee 1149.1 interface timing figure 18. jtag test clock input timing table 52. jtag interface timing 1 1 these specifications apply to jtag boundary scan only. jtag timing specified at v dd = 3.0 v to 3.6 v, t a = ?40 to 105 c, and cl = 50 pf with src = 0b01. num symbol c characteristic min max unit specid 1t jcyc cc 2 2 parameter values guaranteed by design. d tck cycle time 100 ? ns a1.1 2t jdc cc 2 d tck clock pulse width (measured at v dd /2) 40 60 ns a1.2 3t tckrise cc 2 d tck rise and fall times (40% ? 70%) ? 3 ns a1.3 4t tmss, t tdis cc 2 d tms, tdi data setup time 5 ? ns a1.4 5t tmsh, t tdih cc 2 d tms, tdi data hold time 25 ? ns a1.5 6t tdov cc 2 d tck low to tdo data valid ? 35 ns a1.6 7t tdoi cc 2 d tck low to tdo data invalid 0 ? ns a1.7 8t tdohz cc 2 d tck low to tdo high impedance ? 30 ns a1.8 9t bsdv cc 2 d tck falling edge to output valid ? 35 ns a1.9 10 t bsdvz cc 2 d tck falling edge to output valid out of high impedance ? 50 ns a1.10 11 t bsdhz cc 2 d tck falling edge to output high impedance ? 50 ns a1.11 12 t bsdst cc 2 d boundary scan input valid to tck rising edge 50 ? ns a1.12 13 t bsdht cc 2 d tck rising edge to boundary scan input invalid 50 ? ns a1.13 tck 1 2 2 3 3
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 103 figure 19. jtag test access port timing tck 4 5 6 7 8 tms, tdi tdo
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 104 figure 20. jtag boundary scan timing tck output signals input signals output signals 9 10 11 12 13
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 105 4.18.2 nexus debug interface figure 21. nexus output timing table 53. nexus debug port timing 1 1 jtag specifications in this table apply when used for debug functionality. all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. nexus timing specified at v dd = 3.0 v to 3.6 v, t a = ?40 to 105 c, and cl = 50 pf (cl = 30 pf on mcko), with src = 0b10 for mcko and 0b11 for others. num symbol c characteristic min max unit specid 1t mcyc cc 2 2 parameter values guaranteed by design. d mcko cycle time 15 ? ns a2.1 2t mdc cc 2 d mcko duty cycle 40 60 % a2.2 3t mdov cc 2 d mcko low to mdo data valid 3 3 mdo, mseo , and evto data is held valid until next mcko low cycle. 0.1 0.2 t mcyc a2.3 4t mseov cc 2 d mcko low to mseo data valid 3 0.1 0.2 t mcyc a2.4 5t evtov cc 2 d mcko low to evto data valid 3 0.1 0.2 t mcyc a2.5 6t evtipw cc 2 d evti pulse width 4 ? t tcyc a2.6 7t evtopw cc 2 d evto pulse width 1 ? t mcyc a2.7 8t tcyc cc 2 d tck cycle time 4 4 the system clock frequency needs to be th ree times faster that the tck frequency. nexus dual data rate is not supported. the timings are me ntioned for dedicated pins on 416tepbga package. the max value for #2, 3, and 4 above, are 0.3 of tmcyc for shared nexus ports. 100 ? ns a2.8 9t tdc cc 2 d tck duty cycle 40 60 % a2.9 10 t ntdis, t ntmss cc 2 d tdi, tms data setup time 25 ? ns a2.10 11 t ntdih, t ntmsh cc 2 d tdi, tms data hold time 5 ? ns a2.11 12 t jov cc 2 d tck low to tdo data valid 0 35 ns a2.12 1 2 4 5 mcko mdo mseo evto output data valid 3
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 106 figure 22. nexus tck timing figure 23. nexus tdi, tms, tdo timing 4.18.3 interface to tft lcd panels (dcu3 and dculite) figure 24 depicts the lcd interface timing for a generic active matrix color tft panel. in this figure signals are shown with pos itive polarity. the sequen ce of events for active matrix interface timing is: tck 8 9 9 tdo 10 11 tms, tdi 12 tck
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 107 ? pclk latches data into the panel on its positive edge (w hen positive polarity is selected). in active mode, pclk runs continuously. this signal frequency could be from 5 to 66 mhz depending on the panel type. ? hsync causes the panel to start a new line. it always encompasses at least one pclk pulse. ? vsync causes the panel to start a new frame. it always encompasses at least one hsync pulse. ? de acts like an output enable signal to the lcd pa nel. this output enables the data to be shifted onto the display. when disabled, the data is invalid and the trace is off. figure 24. tft lcd interface timing overview 1 4.18.3.1 interface to tft lcd panels?pixel level timings figure 25 depicts the horizontal timing (tim ing of one line), including bot h the horizontal sync pulse and data. all parameters shown in the diagram are programmable. this tim ing diagram corres ponds to positive polarity of the pclk signal (meaning the data and sync signals change on the rising edge) and active-high polarity of the hsync, vsync and de signals. the user can select the polarity of the hsync and vsync signals via the syn_pol regi ster, whether active-high or active- low. the default is active-high. the de signal is always active-high. pixel clock inversion and a flexible programmabl e pixel clock delay are also supported. they are programmed via the dcu clock confide register (dccr) in the system clock module. the delta_x and delta_y parameters are prog rammed via the disp_size register. the pw_h, bp_h and fp_h parameters are programmed via th e hsyn para register. the pw_v, bp_v and fp_v parameters are programmed vi a the vsyn_para register. 1. in figure 24 , the ?ld[23:0]? signal is ?line data,? an aggregatio n of the dcu?s rgb signals?r[0:7], g[0:7] and b[0:7]. line 1 line 2 line 3 line 4 line n-1 line n vsync hsync hsync de pclk ld[23:0] 2 13 m-1m
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 108 figure 25. horizontal sync timing table 54. lcd interface timing parameters?horizontal and vertical num symbol c characteristic value unit specid 1t pcp cc 1 1 parameter values guaranteed by design. d display pixel clock period 31.25 ns a3.1 2t pwh cc 1 d hsync pulse width pw_h t pcp ns a3.2 3t bph cc 1 d hsync back porch width bp_h t pcp ns a3.3 4t fph cc 1 d hsync front porch width fp_h t pcp ns a3.4 5t sw cc 1 d screen width delta_x t pcp ns a3.5 6t hsp cc 1 d hsync (line) period (pw_h + bp_h + fp_h + delta_x ) t pcp ns a3.6 7t pwv cc 1 d vsync pulse width pwv t hsp ns a3.7 8t bpv cc 1 d vsync back porch width bp_v t hsp ns a3.8 ?t fpv cc 1 d vsync front porch width fp_v t hsp ns a3.9 ?t sh cc 1 d screen height delta_y t hsp ns a3.10 ?t vsp cc 1 d vsync (frame) period (pw_v + bp_v + fp_v + delta_y ) t hsp ns a3.11 start of line pclk ld[23:0] hsync de t pwh t bph t hsp t sw t pcp t fph 1 2 3 delta_x invalid data invalid data
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 109 figure 26. vertical sync pulse 4.18.3.2 interface to tft lcd panels?access level table 55. lcd interfac e timing parameters 1,2,3,4 ?access level 1 the characteristics in this table are based on the assumption that data is output at +ve edge and displays latch data on ?ve edge. 2 intrabit skew is less than 2 ns. 3 load cl = 50 pf for frequency up to 20 mhz. 4 load cl = 25 pf for display freq from 20 to 32 mhz. num symbol c characteristic min. value typical value max. value unit specid 1t ckp cc 5 5 parameter values guaranteed by design. d pdi clock period 31.25 ? ? ns a3.12 2t chd cc 5 d duty cycle 40 ? 60 % a3.13 3t dsu cc 5 d interface data setup time 6 ? ? ns a3.14 4t dhd cc 5 d pdi interface data access hold time 1 ? ? ns a3.15 5t csu cc 5 d pdi interface control signal setup time 3 ? ? ns a3.16 6t chd cc 5 d pdi interface control signal hold time 1 ? ? ns a3.17 7?cc 5 d tft interface data valid after pixel clock ? ? 6 ns a3.18 8?cc 5 d tft interface hsync valid after pixel clock ? ? 5 ns a3.19 9?cc 5 d tft interface vsync valid after pixel clock ? ? 5.5 ns a3.20 10 ? cc 5 d tft interface de valid after pixel clock ? ? 5.6 ns a3.21 11 ? cc 5 d tft interface hold time for data and control bits 2 ? ? ns a3.22 12 ? cc 5 d relative skew between the data bits ? ? 3.7 ns a3.23 start of frame hsync ld[23:0] hsync de t pwv t bpv t vsp t hcp t fpv 1 2 3 delta_y invalid data invalid data (line data) t sh
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 110 figure 27. lcd interface timing parameters?access level 4.18.4 rsds interface to tft lcd panels table 56. rsds electrical characteristics symbol c parameter conditions 1 1 v dda = 3.3 v 10% t a = ?40 to 105 c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit specid min typ max avdd sr p voltage on vsse_a pin with respect to ground (v ss ) ?3.03.33.6va4.1 i ddtx sr p current consumption: rsds trans- mitter ? single cell ??2.7?maa4.2 i ddpd sr p power down current ? ? 10 ? a a4.3 i ddbg sr p current consumption of bandgap and buffer ?? 100 ? a a4.4 fmax sr p data frequency ? ? 60 85 mhz a4.5 v od sr p differential output voltage r l = 100 ohms ? 200 400 mv a4.6 v off sr p offset voltage v cm 5% 0.5 1.2 1.5 v a4.7 t r / t f sr p output rise / fall times 20% to 80%, v od =200mv, c l = 5pf ? 500 ? ps a4.8 t xdelay sr p tx delay ? ? 3 ? ns a4.9 sr p termination resistance (external) 5% variation ? 100 ? ohms a4.10 sr p transmitter settling time after power down, high to low ? 10 ? s a4.11 sr d transmitter delay data in to tx out ? 8 ? ns a4.12 hsync vsync dde pclk ld[23:0] t ckh t ckl t chd t csu t dhd t dsu
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 111 figure 28. tcon/rsds timing diagram
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 112 4.18.5 dram interface ddr interface specification from ?mcd ? 32 bit automotiv e mcu ? cmos090lp2? i/o pad specification revisi on 1.5 ? may14th 2008. this device supports sdr, ddr1, dd r2 half and full strengths, as well as lpddr half and full speeds. table 57 shows the sre settings for the different modes. note: the specifications given in table 58 are preliminary. table 57. pad mode configurations ipp_sre[2:0] mode 000 1.8v lpddr half speed 001 1.8v lpddr full speed 010 1.8v ddr2 half strength 011 2.5v ddr1 100 not supported 101 not supported 110 1.8v ddr2 full strength 111 sdr table 58. lpddr, ddr, and ddr2 (d dr2-250) sdram timing specifications 1 2 3 1 at recommended operating conditions with v dde_dr of 5%. 2 v dde_dr value is 1.8 for ddr2 mode, 2.5 v for ddr1 mode, and 1.8 v for lpddr mode. 3 c z at ?40, 140, 25 o c. no. symbol parameter min max unit 1 f cc frequency of operation (clock period) n/a 125 mhz 1.1 t ck cc clock period n/a 8 ns 2 v ix-ac cc mck ac differential crosspoint voltage 4 v dde_dr 0.5 ?0.1 v dde_dr 0.5 +0.1 v 3 t ch cc ck high pulse width 4, 5 0.47 0.53 tck 4 t cl cc ck low pulse width 4, 5 0.47 0.53 tck 5 t dqss cc skew between mck and dqs transitions 5, 6 150 150 ps 6 t os(base) cc address and control output setup time relative to mck rising edge 5, 6 (tck/2) ? 1000 n/a ps 7 t oh(base) cc address and control output hold time relative to mck rising edge 5, 6 (tck/2) + 1000 n/a ps 8 t ds1(base) cc dq and dm output setup time relative to dqs 5, 6 (tck/4) ? 750 n/a ps 9 t dh1(base) cc dq and dm output hold time relative to dqs 5, 6 (tck/4) + 750 n/a ps 10 t dqsq cc dqs-dq skew for dqs and associated dq inputs 5 ?(tck/4) ? 600 (tck/4) ? 600 ps 11 t dqsen cc dqs window start position related to cas read command 4, 5, 6, 7, 8 tbd tbd ps
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 113 4.18.5.1 2.5v ddr1 the sstl_2 differential input switch point is at vref = 0.50 vddet. note that the jedec sstl_2 sp ecifications (jesd8-9b) fo r an sstl interface for class ii operation supersedes any specification in this document. the sstl_2 class ii output with ipp_sre[2:0] set to enabling ss tl_2 2.5v ddr1 mode, at the destination, have a rise/fall time (10?90%) between 1 ns and 2 ns over process, voltage, and temp erature driving a 70 ohm transmission line with 0.167 ns td terminated at the destination with 70 ohms to vtt (0.5 vddet) with 4.0 pf, representing the ddr input capacitance. 4 measured with clock pin loaded with differential 100 ohm termination resistor. 5 all transitions measur ed at mid-supply ( v dde_dr /2). 6 measured with all outputs except the clock lo aded with 50 ohm termination resistor to v dde_dr /2. 7 in this window, the first rising edge of dqs should occur. fr om the start of the window to dqs rising edge, dqs should be low. 8 window position is given for t dqsen = 2.0 t ck . for other values of t dqsen , window position is shifted accordingly. table 59. sstl_2 class ii 2.5v ddr dc specifications symbol c parameter condition m in nom max units notes specid vddet p i/o supply voltage ? 2.30 2.50 2.70 v jesd8-9b a5.1 vdd p core supply voltage ? 1.08 1.20 1.32 v ? a5.2 vref(dc) p input reference voltage ? 1.13 1.25 1.38 v jesd8-9b a5.3 vtt p termination voltage ? vref ? 0.04 vref vref + 0.04 v jesd8-9b a5.4 v ih(dc) c dc input logic high ? vref + 0.15 ? vddet + 0.3 v jesd8-9b a5.5 v il(dc) c dc input logic low ? ?0.3 ? vref ? 0.15 v jesd8-9b a5.6 v ih(ac) c ac input logic high ? vref + 0.31 ? ? v jesd8-9b a5.7 v il(ac) c ac input logic low ? ? ? vref ? 0.31 v jesd8-9b a5.8 i in p pad input leakage current ? ? ? 10 a ? a5.9 v oh c output high voltage level ? vddet ? 0.35 ? ? v ? a5.10 v ol c output low voltage level ? ? ? 0.35 v ? a5.11 i oh(dc) c output min source dc current vout = voh ?16.2 ? ? ma vddet = 2.3 v voh = 1.95 v a5.12 i ol(dc) c output min sink dc current vout = vol 16.2 ? ? ma vddet = 2.3 v vol = 0.35 v a5.13
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 114 figure 29. sstl_2 class ii test load 4.18.5.2 1.8v ddr2 the sstl_18 differential input switch point is at vref = 0.50 vddet. note that the jedec sstl_18 specificati ons (jesd8-15a) for an sstl interface fo r class ii operation supersedes any specification in this document. the sstl_18 class ii output with ipp_sre[2:0] set to enabling sstl_ 2 1.8v ddr2 mode, at the destination, have a rise/fall time (10?90%) between 0.4 ns and 1.0 ns over process, voltage, and temperature driving a 70 ohm transmission line with 0.167 ns table 60. sstl_18 class ii 1. 8v ddr2 dc specifications symbol c parameter condition min nom max units notes specid vddet p i/o supply voltage ? 1.7 1.8 1.9 v jesd8-15a a5.14 vdd p core supply voltage ? 1.08 1.2 1.32 v ? a5.15 vref(dc) p input reference voltage ? 0.833 0.9 1.0869 v jesd8-15a a5.16 vtt p termination voltage ? vref ? 0.04 vref vref + 0.04 v jesd8-15a a5.17 v ih(dc) c dc input logic high ? vref + 0.125 ? vddet + 0.3 v jesd8-15a a5.18 v il(dc) c dc input logic low ? ?0.3 ? vref ? 0.125 v jesd8-15a a5.19 v ih(ac) c ac input logic high ? vref + 0.25 ? ? v jesd8-15a a5.20 v il(ac) c ac input logic low ? ? ? vref ? 0.25 v jesd8-15a a5.21 i in p pad input leakage current ? ? ? 10 a ? a5.22 v oh c output high voltage level ? vddet ? 0.28 ? ? v ? a5.23 v ol c output low voltage level ? ? ? 0.28 v ? a5.24 i oh(dc) c output min source dc current vout = voh ?13.4 ? ? ma jesd8-15a vddet = 1.7 v voh = 1.42 v a5.25 i ol(dc) c output min sink dc current vout = vol 13.4 ? ? ma jesd8-15a vddet = 1.7 v vol = 0.28 v a5.26 pad ipp_do z 0 =70 td= 0.167ns 4pf vtt 70 ohms pad_st/pad_st_odt
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 115 td terminated at the destination with 70 ohms to vtt (0.5 vddet) with 4.0 pf, representing the ddr2 input capacitance. see figure 30 (sstl_18 class ii test load) . figure 30. sstl_18 class ii test load 4.18.5.3 1.8v lpddr note that the final jedec lpddr sdram specifications (jesd79-4) for lpddr operation supers edes any specification in this document. the sstl_18 output with ipp_sre[2:0] set to enabling 1.8v lpddr mode, at the destination, have a rise/fall time (10?90%) between 0.4 ns and 1.0 ns over process, vo ltage, and temperature driving a 70 ohm transmission line with 0.167 ns td terminated at the destination with 70 ohms to vtt (0.5 vddet) with 4.0 pf, representing the ddr input capacitance. see figure 30 (sstl_18 class ii test load) . table 61. 1.8v lpddr dc specifications symbol c parameter condition min nom max units notes specid vddet p i/o supply voltage ? 1.7 1.8 1.9 v jesd79-4 a5.27 vdd p core supply voltage ? 1.08 1.2 1.32 v ? a5.28 data inputs (dq, dm, dqs) a5.29 v ih(dc) c dc input logic high ? vddet 0.7 ? vddet+0.3 v jesd79-4 a5.30 v il(dc) c dc input logic low ? ?0.3 ? vddet 0.3 v jesd79-4 a5.31 v ih(ac) c ac input logic high ? vddet 0.8 ? vddet + 0.3 v jesd79-4 a5.32 v il(ac) c ac input logic low ? ?0.3 ? vddet 0.2 v jesd79-4 a5.33 data outputs (dq, dqs) a5.34 v oh c output high voltage level ioh = ?0.1ma vddet 0.9 ? ? v jesd79-4 a5.35 v ol c output low voltage level iol = 0.1ma ? ? vddet 0.1 v jesd79-4 a5.36 pad ipp_do z 0 =70 td= 0.167ns 4pf vtt 70 pad_st/pad_st_odt
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 116 4.18.6 video input unit timing figure 31. viu2 timing diagram 4.18.7 external interrupt (irq) and no n-maskable interrupt (nmi) timing figure 32. irq and nmi timing table 62. viu2 timing parameters parameter c description min typ max unit specid f pix_ck d viu2 pixel clock frequency ? ? 64 mhz a6.1 t dsu d viu2 data setup time 4 ? ? ns a6.2 t dhd d viu2 data hold time 1 ? ? ns a6.3 table 63. irq and nmi timing num symbol c characteristic min. value max. value unit specid 1t ipwl cc 1 1 parameter values guaranteed by design. d irq/nmi pulse width low 200 ? ns a7.1 2t ipwh cc 1 d irq/nmi pulse width high 200 ? ns a7.2 3t icyc cc 1 d irq/nmi edge to edge time 2 2 applies when irq/nmi pins are configured for ri sing edge or falling edge events, but not both. 400 ? ns a7.3 f pix_clk t dhd t dsu clock data 1,2 3 1,2
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 117 4.18.8 emios timing 4.18.9 flexcan timing the can functions are availa ble as tx pins at normal i/o pads and as rx pins at the always on domain. there is no filter for the wakeup dominant pulse . any high-to-low edge can cause wakeup if configured. 4.18.10 deserial serial peripheral interface (dspi) table 64. emios timing 1 1 emios timing specified at f sys = 64 mhz, v dd12 = 1.14 v to 1.32 v, vdde_x = 3.0 v to 5.5 v, t a = ?40 to 105 c, and cl = 50 pf with src = 0b00. num symbol c characteristic min. value 2 2 there is no limitation on the peripheral for setting the minimum pu lse width, the actual width is restricted by the pad delays. refer to the pad specification section for the details. max. value unit specid 1t mipw cc 3 3 parameter values guaranteed by design. d emios input pulse width 4 ? t cyc a8.1 2t mopw cc 3 d emios output pulse width 1 ? t cyc a8.2 table 65. flexcan timing 1 1 flexcan timing specified at f sys = 64 mhz, v dd12 = 1.14 v to 1.32 v, vdde_x = 3.0 v to 5.5 v, t a = ?40 to 105 c, and cl = 50 pf with src = 0b00. num symbol c characteristic min. value max. value unit specid 1t canov cc 2 2 parameter values guaranteed by design. d ctnx output valid after clkout rising edge (output delay) ? 22.48 ns a10.1 2t cansu cc 2 d cnrx input valid to clkout rising edge (setup time) ? 12.46 ns a10.2 table 66. dspi timing 1 num symbol c characteristic min max unit specid 1t sck cc 2 d sck cycle time 3,4 60 5 ? ns a11.1 2t csc cc 2 d pcs to sck delay 6 ? ? ns a11.2 3t asc cc 2 d after sck delay 7 20 ? ns a11.3 4t sdc cc 2 d sck duty cycle t sck /2?2ns t sck /2 + 2ns ns a11.4 5t a cc 2 d slave access time (pcsx active to sout driven) ? 25 ns a11.5 6t dis cc 2 d slave sout disable time (pcsx inactive to sout high-z or invalid) ? 25 ns a11.6
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 118 7t sui cc 2 d data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 8 master (mtfe = 1, cpha = 1) 20 10 5 35 ? ? ? ? ns ns ns ns a11.7 8t hi cc 2 d data hold time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 8 master (mtfe = 1, cpha = 1) ?4 10 26 ?4 ? ? ? ? ns ns ns ns a11.8 9t suo cc 2 d data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha=0) master (mtfe = 1, cpha=1) ? ? ? ? 15 20 30 15 ns ns ns ns a11.9 10 t ho cc 2 d data hold time for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) ?15 5.5 0 ?15 ? ? ? ? ns ns ns ns a11.10 1 dspi timing specified at vdde_x = 3.0 v to 3.6 v, t a = ?40 to 105 c, and cl = 50 pf with src = 0b10. 2 parameter values guaranteed by design. 3 the minimum sck cycle time restricts the baud rate selection for given system clock rate. 4 the actual minimum sck cycle time is limited by pad performance. 5 maximum clock possible is system clock/2. 6 the maximum value is programmable in dspi_ctarx[pssck] and dspi_ctarx[cssck], program pssck=2 & cssck = 2 7 the maximum value is programmable in dspi_ctarx[pasc] and dspi_ctarx[asc] 8 this delay value is corresponding to smpl_pt=00b which is bit field 9 and 8 of dspi_mcr register. table 66. dspi timing 1 (continued) num symbol c characteristic min max unit specid
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 119 figure 33. dspi classic spi timing ? master, cpha = 0 figure 34. dspi classic spi timing ? master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 7 10 1 9 8 4 sck output (cpol=0) (cpol=1) 3 2 data last data first data sin sout 10 9 8 last data data first data sck output sck output pcsx 7 (cpol=0) (cpol=1)
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 120 figure 35. dspi classic spi timing ? slave, cpha = 0 figure 36. dspi classic spi timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout pcsx 4 5 6 7 9 8 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 5 6 7 10 9 8 last data last data sin sout pcsx first data first data data data sck input sck input (cpol=0) (cpol=1)
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 121 figure 37. dspi modified transfer format timing ? master, cpha = 0 figure 38. dspi modified transfer format timing ? master, cpha = 1 pcsx 3 1 4 8 4 7 10 9 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) pcsx 8 7 10 9 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1)
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 122 figure 39. dspi modified transfer format timing ? slave, cpha = 0 figure 40. dspi modified transfer format timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout pcsx 4 5 6 7 9 8 sck input first data last data sck input 2 (cpol=0) (cpol=1) 10 5 6 7 10 9 8 last data last data sin sout pcsx first data first data data data sck input sck input (cpol=0) (cpol=1)
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 123 4.18.11 i 2 c timing table 67. i 2 c input timing specifications?scl and sda num symbol c characteristic min. value max. value unit specid 1?cc 1 1 parameter values guaranteed by design. d start condition hold time 2 ? ip-bus cycle 2 2 inter peripheral clock is the clock at which the i 2 c peripheral is working in the device a12.1 2?cc 1 d clock low time 8 ? ip-bus cycle 2 a12.2 4?cc 1 d data hold time 0.0 ? ns a12.3 6?cc 1 d clock high time 4 ? ip-bus cycle 2 a12.4 7?cc 1 d data setup time 0.0 ? ns a12.5 8?cc 1 d start condition setup time (for repeated start condition only) 2 ? ip-bus cycle 2 a12.6 9?cc 1 d stop condition setup time 2 ? ip-bus cycle 2 a12.7 table 68. i 2 c output timing specifications?scl and sda num symbol c characteristic min. value max. value unit specid 1 1 1 programming ibfd (i 2 c bus frequency divider) with the maximum frequency re sults in the minimum output timings listed. the i 2 c interface is designed to scale the data transition time, moving it to the middle of the scl low period. the actual position i s affected by the prescale and division values programmed in ifdr. ?cc 2 2 parameter values guaranteed by design. d start condition hold time 6 ? ip-bus cycle 3 3 inter peripheral clock is the clock at which the i 2 c peripheral is working in the device a12.8 2 1 ?cc 2 d clock low time 10 ? ip-bus cycle 2 a12.9 3 4 4 because scl and sda are open-drain-type outputs, which the pr ocessor can only actively drive low, the time scl or sda takes to reach a high level depends on external signal capacitance and pullup resistor values. ?cc 2 d scl/sda rise time ? 99.6 ns a12.10 4 1 ?cc 2 d data hold time 7 ? ip-bus cycle 2 a12.11 5 1 ?cc 2 d scl/sda fall time ? 99.5 ns a12.12 6 1 ?cc 2 d clock high time 10 ? ip-bus cycle 2 a12.13 7 1 ?cc 2 d data setup time 2 ? ip-bus cycle 2 a12.14 8 1 ?cc 2 d start condition setup time (for repeated start condition only) 20 ? ip-bus cycle 2 a12.15 9 1 ?cc 2 d stop condition setup time 10 ? ip-bus cycle 2 a12.16
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 124 figure 41. i 2 c input/output timing 4.18.12 quadspi timing the following notes apply to table 69 and table 70 : ? all data is based on a negative edge data launch from px d20 and a positive edge data capture, as shown in the timing diagrams in this section. ? the supply conditions, over a temperature range of ?45 ? c to 125 ? c/150 ? c, are as follows: ? i/o voltage: 3.0 v, core supply: 1.2 v ? i/o voltage: 3.3 v, core supply: 1.2 v ? i/o voltage: 3.6 v, core supply: 1.2 v ? the actual frequency at which the device can work will be a combination of this data and the clock pad profile. ? all measurements are considering 70 % of vdde levels for clock pin and 50% of vdde level for data pins. ? timings assume a setting of 0x0000_000x for qspi_smp r register (see the reference manual for details). ? a negative value of hold is an indication of pad delay on the clock pad (delay b/w actual edge capturing data in the device vs. edge appearing at the pin). ? measurements are with a load of 50 pf on output pins ? the clock profile is measured at 30% to 70% levels of vdde. the numbers in figure 42 and figure 43 correspond to events as described in table 70 . table 69. quadspi timing specifications, maximum temperature 125 ? c symbol c parameter value unit specid min typ max tcq cc t clock to q delay 3.8 5.3 12.1 ns a13.1 ts cc t setup time for incoming data 7.6 9 13.2 ns a13.2 th cc t hold time requirement for incoming data ?13 ?8.5 ?7.5 ns a13.3 tr cc t clock pad rise time 0.5 0.7 1.0 ns a13.4 tf cc t clock pad fall time 0.8 0.8 1.2 ns a13.5 scl sda 1 2 4 6 7 8 9 5 3
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 125 figure 42. quadspi output timing figure 43. quadspi input timing table 70. quadspi timing events number event 1 last address out 2 address captured at flash memory 3 data out from flash memory 4 ideal data capture edge 5 delayed data capture edg e with qspi_smpr=0x0000_000x 6 delayed data capture edg e with qspi_smpr=0x0000_002x 7 delayed data capture edg e with qspi_smpr=0x0000_004x 8 delayed data capture edg e with qspi_smpr=0x0000_006x sck t cq do 1. last address out 1 t cq sck t h t s do di 1. last address out 2. address captured at flash 3. data out from flash 4. ideal data capture edge 5. delayed data capture edge with qspi_smpr=0x0000_000x 6. delayed data capture edge with qspi_smpr=0x0000_002x 7. delayed data capture edge with qspi_smpr=0x0000_004x 8. delayed data capture ed ge with qspi_smpr=0x0000_006x 2 3 4 5 6 7 8 1
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 126 figure 44. quadspi clock profile 4.18.13 tcon/rsds timing the following notes apply to table 71 : ? measurement condition: vdde/vdd33 = 3.3 v 10%, vdd = 1.2 v 10%, vss/vsse = 0 v, t = ?40 to 105c ? termination: 100 ? 5% ? vrefh_rsds terminations of 47 ? f table 71. tcon/rsds timing symbol c parameter condition value unit specid min typ max v od cc c differential output volt age rsds mode 391 ? 471 mv a14.1 v os cc c common mode voltage 100 ? termination between pad_p and pad_n 1.17 ? 1.4 v a14.2 tr cc c rise time transition from 20% to 80% 606 ? 844 ps a14.3 tf cc c fall time transition from 20% to 80% 607 ? 842 ps a14.4 tplh cc d propagation delay, low to high ? ? 2.65 ? ns a14.5 tphl cc d propagation delay, high to low ? ? 2.47 ? ns a14.6 tdz cc d start-up time ? ? 200 ? ? sa14.7 tskew 1 2 3 1 there are eight programmable bits to provide 256 differen t skew numbers with various combinations of these bits. 2 default value of all the eight skew options are all ?1?. 3 all ?0? combination of eight bits is not valid. cc c skew between different rsds lines max and min skew between clock and data pads ???psa14.8 t r t f 70% 30% vdde sck
electrical characteristics PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 127 figure 45. rise/fall transition, part 1 figure 46. rise/fall transition, part 2 figure 47. illustration of tr, tf, and v od pad_p - pad_n 80% +v od ?v od 20% t r t f 0v differential
package mechanical data PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 128 5 package mechanical data 6 ordering information figure 48. PXD20 orderable part number description table 72. PXD20 orderable part number summary part number flash/sram package speed (mhz) mPXD2020vlu125 2 mb / 64 kb 176 lqfp (24 mm x 24 mm) 125 mPXD2020vvu125 2 mb / 64 kb 416 pbga (27 mm x 27 mm) 125 mPXD2020vlt125 2 mb / 64 kb 208 lqfp (28 mm x 28 mm) 125 mpx 20 note: not all options are available on all devices. see ta bl e 7 2 for more information. d qualification status brand family class flash memory size temperature range v = ?40 c to 105 c operating frequency 80 = 80 mhz tape and reel status r = tape and reel (blank) = trays qualification status p = pre-qualification (engineering samples) m = fully spec. qualified, general market flow s = fully spec. qualified, automotive flow 20 v temperature range lt package identifier 125 r operating frequency tape and reel indicator package identifier lu = 176 lqfp 120 = 120 mhz (ambient) lt = 208 lqfp family d = display graphics n = connectivity/network r = performance/real time control s=safety flash memory size 05 = 512 kb 10 = 1 mb vu = 416 pbga
revision history PXD20 microcontroller data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 129 7 revision history table 73. revision history revision date description 1 30 sep 2011 initial release. 2 27 apr 2012 editorial updates and impr ovements throughout the document. in figure 4 (416 tepbga pinout) , corrected pin p25 to vss. in section 3, system design information , added figure 6 (power-up sequencing) and figure 7 (power-down sequencing) . in table 10 (recommended operating conditions (3.3 v)) , changed maximum tj from 150 o c to 140 o c. in table 11 (recommended operating conditions (5.0 v)) , changed maximum tj from 150 o c to 140 o c. in table 16 (voltage regulator electrical characteristics) : ? changed maximum tj from 150 o c to 140 o c. ? changed v dd12 post-trimming minimum value from 1.270 v to 1.26 v and maximum value from 1.280 v to 1.29 v. ? removed footnote: ?all values in this table are preliminary.? in section 4.7.1, voltage regulator electrical characteristics . added table 17 (low-power voltage regulator electrical characteristics) and table 18 (ultra low-power voltage regulator electrical characteristics) . in table 19 (low voltage monitor electrical characteristics) , updated the following values: ? v lv d h v 3 h maximum from 2.8 v to 2.9 v ? v lv d h v 3 l minimum from 2.7 v to 2.5 v ? v lv d h v 5 h maximum from 4.37 v to 4.4 v ? v lv d h v 5 l minimum from 4.2 v to 3.9 v in table 20 (dc electrical characteristics) : ? updated i ddrun typical values for dual display drive from 235 to 275 ma; for single display drive from 306 to 240 ma. ? updated typical i ddhalt current at 25 o c from 12.67 ma to 17.5 ma. ? updated typical i ddhalt current at 105 o c from 33.1 ma to 35 ma. ? updated maximum i ddhalt current at 25 o c from 18.26 ma to 21.5 ma. ? updated maximum i ddhalt current at 105 o c from 36.41 ma to 43.5 ma. ? in i ddhalt specification, changed t b = 105 o c to t a =105 o c. in table 40 (fast internal oscillator electrical characteristics) , removed ? rcmtrim specification. in table 41 (slow internal rc oscillator electrical characteristics) , removed ? rcmtrim specification. in table 44 (adc electrical characteristics) , added offset error value of 0.5 typical, and gain error value of 0.6 typical. removed minimum and maximum values for both specifications. in section 4.18.5, dram interface : ? added table 58 (lpddr, ddr, and ddr2 (ddr2-250) sdram timing specifications) . ? removed table 56 (ac specs for sdr mode (v dde_dr = 3.3 v)) , ta bl e 5 7 ( ac specs for ddr2 mode (v dde_dr = 1.8 v)) , table 58 (ac specs for ddr1 mode (v dde_dr = 2.5 v)) , and table 59 (ac specs for lpmddr mode (v dde_dr = 1.8 v)) .
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